219 lines
7.7 KiB
C++
219 lines
7.7 KiB
C++
/**
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* Copyright (c) 2011-2018 Bill Greiman
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* This file is part of the SdFat library for SD memory cards.
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*
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* MIT License
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "SdSpiDriver.h"
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#if defined(__SAM3X8E__) || defined(__SAM3X8H__)
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/** Use SAM3X DMAC if nonzero */
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#define USE_SAM3X_DMAC 1
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/** Use extra Bus Matrix arbitration fix if nonzero */
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#define USE_SAM3X_BUS_MATRIX_FIX 0
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/** Time in ms for DMA receive timeout */
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#define SAM3X_DMA_TIMEOUT 100
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/** chip select register number */
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#define SPI_CHIP_SEL 3
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/** DMAC receive channel */
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#define SPI_DMAC_RX_CH 1
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/** DMAC transmit channel */
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#define SPI_DMAC_TX_CH 0
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/** DMAC Channel HW Interface Number for SPI TX. */
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#define SPI_TX_IDX 1
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/** DMAC Channel HW Interface Number for SPI RX. */
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#define SPI_RX_IDX 2
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//------------------------------------------------------------------------------
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/** Disable DMA Controller. */
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static void dmac_disable() {
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DMAC->DMAC_EN &= (~DMAC_EN_ENABLE);
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}
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/** Enable DMA Controller. */
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static void dmac_enable() {
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DMAC->DMAC_EN = DMAC_EN_ENABLE;
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}
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/** Disable DMA Channel. */
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static void dmac_channel_disable(uint32_t ul_num) {
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DMAC->DMAC_CHDR = DMAC_CHDR_DIS0 << ul_num;
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}
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/** Enable DMA Channel. */
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static void dmac_channel_enable(uint32_t ul_num) {
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DMAC->DMAC_CHER = DMAC_CHER_ENA0 << ul_num;
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}
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/** Poll for transfer complete. */
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static bool dmac_channel_transfer_done(uint32_t ul_num) {
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return (DMAC->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) ? false : true;
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}
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//------------------------------------------------------------------------------
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void SdSpiAltDriver::begin(uint8_t csPin) {
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m_csPin = csPin;
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pinMode(m_csPin, OUTPUT);
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digitalWrite(m_csPin, HIGH);
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SPI.begin();
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#if USE_SAM3X_DMAC
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pmc_enable_periph_clk(ID_DMAC);
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dmac_disable();
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DMAC->DMAC_GCFG = DMAC_GCFG_ARB_CFG_FIXED;
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dmac_enable();
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#if USE_SAM3X_BUS_MATRIX_FIX
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MATRIX->MATRIX_WPMR = 0x4d415400;
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MATRIX->MATRIX_MCFG[1] = 1;
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MATRIX->MATRIX_MCFG[2] = 1;
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MATRIX->MATRIX_SCFG[0] = 0x01000010;
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MATRIX->MATRIX_SCFG[1] = 0x01000010;
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MATRIX->MATRIX_SCFG[7] = 0x01000010;
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#endif // USE_SAM3X_BUS_MATRIX_FIX
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#endif // USE_SAM3X_DMAC
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}
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//------------------------------------------------------------------------------
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// start RX DMA
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static void spiDmaRX(uint8_t* dst, uint16_t count) {
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dmac_channel_disable(SPI_DMAC_RX_CH);
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_SADDR = (uint32_t)&SPI0->SPI_RDR;
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_DADDR = (uint32_t)dst;
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_DSCR = 0;
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CTRLA = count |
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DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
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DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
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DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING;
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DMAC->DMAC_CH_NUM[SPI_DMAC_RX_CH].DMAC_CFG = DMAC_CFG_SRC_PER(SPI_RX_IDX) |
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DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ASAP_CFG;
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dmac_channel_enable(SPI_DMAC_RX_CH);
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}
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//------------------------------------------------------------------------------
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// start TX DMA
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static void spiDmaTX(const uint8_t* src, uint16_t count) {
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static uint8_t ff = 0XFF;
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uint32_t src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
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if (!src) {
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src = &ff;
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src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
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}
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dmac_channel_disable(SPI_DMAC_TX_CH);
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_SADDR = (uint32_t)src;
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_DADDR = (uint32_t)&SPI0->SPI_TDR;
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_DSCR = 0;
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CTRLA = count |
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DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
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DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
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src_incr | DMAC_CTRLB_DST_INCR_FIXED;
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DMAC->DMAC_CH_NUM[SPI_DMAC_TX_CH].DMAC_CFG = DMAC_CFG_DST_PER(SPI_TX_IDX) |
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DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
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dmac_channel_enable(SPI_DMAC_TX_CH);
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}
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//------------------------------------------------------------------------------
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// initialize SPI controller
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void SdSpiAltDriver::activate() {
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SPI.beginTransaction(m_spiSettings);
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Spi* pSpi = SPI0;
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// Save the divisor
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uint32_t scbr = pSpi->SPI_CSR[SPI_CHIP_SEL] & 0XFF00;
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// Disable SPI
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pSpi->SPI_CR = SPI_CR_SPIDIS;
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// reset SPI
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pSpi->SPI_CR = SPI_CR_SWRST;
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// no mode fault detection, set master mode
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pSpi->SPI_MR = SPI_PCS(SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
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// mode 0, 8-bit,
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pSpi->SPI_CSR[SPI_CHIP_SEL] = scbr | SPI_CSR_CSAAT | SPI_CSR_NCPHA;
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// enable SPI
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pSpi->SPI_CR |= SPI_CR_SPIEN;
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}
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//------------------------------------------------------------------------------
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void SdSpiAltDriver::deactivate() {
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SPI.endTransaction();
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}
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//------------------------------------------------------------------------------
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static inline uint8_t spiTransfer(uint8_t b) {
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Spi* pSpi = SPI0;
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pSpi->SPI_TDR = b;
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while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
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b = pSpi->SPI_RDR;
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return b;
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}
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//------------------------------------------------------------------------------
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/** SPI receive a byte */
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uint8_t SdSpiAltDriver::receive() {
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return spiTransfer(0XFF);
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}
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//------------------------------------------------------------------------------
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/** SPI receive multiple bytes */
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uint8_t SdSpiAltDriver::receive(uint8_t* buf, size_t n) {
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Spi* pSpi = SPI0;
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int rtn = 0;
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#if USE_SAM3X_DMAC
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// clear overrun error
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pSpi->SPI_SR;
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spiDmaRX(buf, n);
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spiDmaTX(0, n);
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uint32_t m = millis();
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while (!dmac_channel_transfer_done(SPI_DMAC_RX_CH)) {
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if ((millis() - m) > SAM3X_DMA_TIMEOUT) {
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dmac_channel_disable(SPI_DMAC_RX_CH);
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dmac_channel_disable(SPI_DMAC_TX_CH);
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rtn = 2;
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break;
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}
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}
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if (pSpi->SPI_SR & SPI_SR_OVRES) {
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rtn |= 1;
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}
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#else // USE_SAM3X_DMAC
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for (size_t i = 0; i < n; i++) {
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pSpi->SPI_TDR = 0XFF;
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while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
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buf[i] = pSpi->SPI_RDR;
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}
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#endif // USE_SAM3X_DMAC
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return rtn;
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}
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//------------------------------------------------------------------------------
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/** SPI send a byte */
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void SdSpiAltDriver::send(uint8_t b) {
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spiTransfer(b);
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}
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//------------------------------------------------------------------------------
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void SdSpiAltDriver::send(const uint8_t* buf , size_t n) {
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Spi* pSpi = SPI0;
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#if USE_SAM3X_DMAC
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spiDmaTX(buf, n);
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while (!dmac_channel_transfer_done(SPI_DMAC_TX_CH)) {}
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#else // #if USE_SAM3X_DMAC
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while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
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for (size_t i = 0; i < n; i++) {
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pSpi->SPI_TDR = buf[i];
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while ((pSpi->SPI_SR & SPI_SR_TDRE) == 0) {}
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}
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#endif // #if USE_SAM3X_DMAC
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while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
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// leave RDR empty
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pSpi->SPI_RDR;
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}
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#endif // defined(__SAM3X8E__) || defined(__SAM3X8H__)
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