424 lines
12 KiB
C
424 lines
12 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file mmu.c
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* @brief MMU code.
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*
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* @addtogroup MMU
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* @{
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "mmu.h"
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#include "armparams.h"
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#include "mcuconf.h"
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#include "ARMCA5.h"
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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#include "cmsis_gcc.h"
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#else
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#include "cmsis_armcc.h"
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#endif
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#include "ccportab.h"
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#if !defined(SAMA_L2CC_ASSUME_ENABLED)
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#define SAMA_L2CC_ASSUME_ENABLED 0
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#endif
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#if !defined(SAMA_L2CC_ENABLE)
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#define SAMA_L2CC_ENABLE 0
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#endif
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#if (SAMA_L2CC_ASSUME_ENABLED && SAMA_L2CC_ENABLE)
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#error "These macros are mutually exclusive"
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#endif
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/*===========================================================================*/
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/* Module local definitions. */
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/*===========================================================================*/
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/*
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* @brief No cacheable memory start address.
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*/
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#define NO_CACHE_MEMORY_START_ADDR ((uint8_t *) 0x27F00000)
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/*===========================================================================*/
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/* Module exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*
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* Use 1MB granularity. It best fits the SAMA5D2 memory layout.
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*
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* The MMU table contains 4096 entries.
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* Each entry in the mmu table (short descriptor, type 1MB section) is 32 bit wide (total 16kB),
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* and is structured in this way (with examples):
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*
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* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
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* |3 2|1 |1|1 |1|1 |1 1|1 1| | | | | | | |
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* |1 0|9 |8|7 |6|5 |4 2|1 0|9|8 5|4 |3|2|1|0 |
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* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
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* | section |NS|0|nG|S|AP[2]|TEX[2:0]|AP[1:0]| |domain|XN|C|B|1|PXN|
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* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
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* | |0 |0|0 |0|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable, write back, no write allocate
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* | |0 |0|0 |1|0 |100 |11 |0|0000 |0 |0|0|1|0 | == normal, no-cacheable
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* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|1|1|0 | == device
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* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|0|1|0 | == strongly-ordered
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* | |0 |0|0 |0|0 |000 |00 |0|0000 |0 |0|0|0|0 | == undefined
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*
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* Domains are 'client'. Accesses are checked against the permission bits in tlb.
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*/
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static uint32_t mmuTable[4096] CC_ALIGN(16384);
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/*===========================================================================*/
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/* Module local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module exported functions. */
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/*===========================================================================*/
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/**
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* @brief Core/MMU Module initialization.
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* @note This function is implicitly invoked on system initialization,
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* there is no need to explicitly initialize the module.
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*
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* @notapi
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*/
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void __core_init(void) {
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uint32_t pm;
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#if ARM_SUPPORTS_L2CC
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#if !SAMA_L2CC_ASSUME_ENABLED
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/* Flush and disable an enabled L2 Cache
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invalidate a disabled L2 Cache.*/
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if ((L2C_310->CONTROL & L2CC_CR_L2CEN) != 0) {
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L2C_Disable();
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L2C_CleanInvAllByWay();
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}
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#endif
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#endif
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/* Flush and disable an enabled L1 D Cache
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Invalidate a disabled L1 D Cache.*/
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pm = __get_SCTLR();
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if ((pm & SCTLR_C_Msk)) {
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L1C_DisableCaches();
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L1C_CleanInvalidateCache(DCISW_CLEAN);
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}
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/* Disable the MMU and invalidate TLB.*/
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MMU_Disable();
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L1C_InvalidateBTAC();
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MMU_InvalidateTLB();
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/*
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* Default, undefined regions
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*/
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for (pm = 0; pm < 4096; ++pm)
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mmuTable[pm] = TTE_SECT_UNDEF;
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/*
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* ROM region
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*
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* 0x00000000
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*/
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mmuTable[0] = TTE_SECT_SECTION(0x00000000) |
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TTE_SECT_MEM_NO_CACHEABLE |
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TTE_SECT_RO_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* NFC SRAM region
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*
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* 0x00100000
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*/
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mmuTable[1] = TTE_SECT_SECTION(0x00100000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* SRAM region
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*
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* 0x00200000
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*/
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mmuTable[2] = TTE_SECT_SECTION(0x00200000) |
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TTE_SECT_MEM_CACHEABLE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_TYPE_SECT;
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/*
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* UDPHS RAM region
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*
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* 0x00300000
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*/
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mmuTable[3] = TTE_SECT_SECTION(0x00300000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* UHPHS region
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*
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* 0x00400000
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*/
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mmuTable[4] = TTE_SECT_SECTION(0x00400000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* UDPHS region
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*
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* 0x00500000
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*/
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mmuTable[5] = TTE_SECT_SECTION(0x00500000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* AXIMX region
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*
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* 0x00600000
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*/
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mmuTable[6] = TTE_SECT_SECTION(0x00600000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* DAP region
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*
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* 0x00700000
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*/
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mmuTable[7] = TTE_SECT_SECTION(0x00700000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* L2CC region, low
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*
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* 0x00a00000
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*/
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mmuTable[0xa] = TTE_SECT_SECTION(0x00a00000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* L2CC region, hi
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*
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* 0x00b00000
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*/
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mmuTable[0xb] = TTE_SECT_SECTION(0x00b00000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* EBI regions
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*
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* 0x10000000 - 0x1fffffff
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*/
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for (pm = 0x100; pm < 0x200; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* DDR regions
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*
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* 0x20000000 - 0x3fffffff
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*/
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for (pm = 0x200; pm < 0x400; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_CACHEABLE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_TYPE_SECT;
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/*
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* DDR AESB regions
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*
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* 0x40000000 - 0x5fffffff
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*/
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for (pm = 0x400; pm < 0x600; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_CACHEABLE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_TYPE_SECT;
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/*
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* EBI 1, 2 and 3 regions
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*
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* 0x60000000 - 0x8fffffff
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*/
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for (pm = 0x600; pm < 0x900; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* QSPI0/1 AESB MEM regions
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*
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* 0x90000000 - 0x9fffffff
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*/
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for (pm = 0x900; pm < 0xa00; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* SDMMC0/1 regions
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*
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* 0xa0000000 - 0xbfffffff
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*/
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for (pm = 0xa00; pm < 0xc00; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_TYPE_SECT;
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/*
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* NFC regions
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*
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* 0xc0000000 - 0xcfffffff
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*/
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for (pm = 0xc00; pm < 0xd00; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* QSPI0/1 MEM regions
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*
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* 0xd0000000 - 0xdfffffff
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*/
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for (pm = 0xd00; pm < 0xe00; pm++)
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mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
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TTE_SECT_MEM_STRONGLY_ORD |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_S | TTE_TYPE_SECT;
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/*
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* Internal peripherals regions
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*
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* 0xf0000000
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* 0xf8000000
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* 0xfc000000
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*/
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mmuTable[0xf00] = TTE_SECT_SECTION(0xf0000000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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mmuTable[0xf80] = TTE_SECT_SECTION(0xf8000000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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mmuTable[0xfc0] = TTE_SECT_SECTION(0xfc000000) |
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TTE_SECT_DEVICE |
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TTE_SECT_RW_ACCESS |
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TTE_SECT_DOM(0x00) |
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TTE_SECT_EXE_NEVER |
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TTE_SECT_S | TTE_TYPE_SECT;
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/* Make a NO CACHE AREA */
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MMU_MemorySection((mmuTable + ((uint32_t)NO_CACHE_MEMORY_START_ADDR >> 20)), NORMAL, NON_CACHEABLE, NON_CACHEABLE);
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/* Invalidate TLB and L1 I cache
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Enable caches and MMU.*/
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MMU_InvalidateTLB();
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__set_TTBR0((uint32_t)mmuTable|0x5B);
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__set_DACR(0x00000001);
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__DSB();
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__ISB();
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/* L1 I cache invalidate and enable.*/
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pm = __get_SCTLR();
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if ((pm & SCTLR_I_Msk) == 0) {
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__set_ICIALLU(0);
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__set_SCTLR(pm | SCTLR_I_Msk);
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}
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/* MMU enable.*/
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pm = __get_SCTLR();
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if ((pm & SCTLR_M_Msk) == 0)
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__set_SCTLR(pm | SCTLR_M_Msk);
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/* L1 D cache enable.*/
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pm = __get_SCTLR();
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if ((pm & SCTLR_C_Msk) == 0) {
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L1C_CleanInvalidateCache(DCISW_INVALIDATE);
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__set_SCTLR(pm | SCTLR_C_Msk);
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}
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#if ARM_SUPPORTS_L2CC
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#if !(SAMA_L2CC_ASSUME_ENABLED) && (SAMA_L2CC_ENABLE)
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if (!(L2C_310->CONTROL & L2CC_CR_L2CEN)) {
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/* High SRAM to L2CC.*/
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SFR->SFR_L2CC_HRAMC = 0x1;
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/* Invalidate and enable L2 cache.*/
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L2C_InvAllByWay();
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L2C_310->AUX_CNT = L2CC_ACR_DPEN | L2CC_ACR_IPEN;
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/* Prefetch control register. Double linefeed, instr and data enabled.*/
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*((uint32_t *)((char *)L2C_310+0x0F60)) = 0x75800001;
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L2C_Enable();
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__DSB();
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__ISB();
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}
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#endif
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#endif
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}
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/** @} */
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