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keyboard/qmk/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h753xx.h

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/**
******************************************************************************
* @file stm32h753xx.h
* @author MCD Application Team
* @version V1.1.0
* @date 31-August-2017
* @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32h753xx
* @{
*/
#ifndef __STM32H753xx_H
#define __STM32H753xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32H7XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
LTDC_IRQn = 88, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
JPEG_IRQn = 121, /*!< JPEG global Interrupt */
MDMA_IRQn = 122, /*!< MDMA global Interrupt */
SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
COMP_IRQn = 137 , /*!< COMP global Interrupt */
LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
SAI4_IRQn = 146, /*!< SAI4 global interrupt */
WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
} IRQn_Type;
/**
* @}
*/
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
/**
* @}
*/
#include "system_stm32h7xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
__IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
__IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
uint32_t RESERVED1; /*!< Reserved, 0x028 */
uint32_t RESERVED2; /*!< Reserved, 0x02C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x044 */
uint32_t RESERVED4; /*!< Reserved, 0x048 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
__IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
__IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
__IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
__IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
__IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
__IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
} ADC_Common_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
__IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
__IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
__IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
__IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
__IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
__IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
__IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
__IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
__IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
__IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
__IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
__IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
__IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
} FDCAN_GlobalTypeDef;
/**
* @brief TTFD Controller Area Network
*/
typedef struct
{
__IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
__IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
__IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
__IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
__IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
__IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
__IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
__IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
__IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
__IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
__IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
__IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
__IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
__IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
__IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
__IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
__IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
__IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
} TTCAN_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
__IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
__IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
__IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
__IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
__IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
} FDCAN_ClockCalibrationUnit_TypeDef;
/**
* @brief Consumer Electronics Control
*/
typedef struct
{
__IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
__IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
} DAC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
__IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
__IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
__IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
__IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
__IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
}DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} BDMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} BDMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief MDMA Controller
*/
typedef struct
{
__IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
}MDMA_TypeDef;
typedef struct
{
__IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
__IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
__IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
__IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
__IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
__IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
__IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
__IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
uint32_t RESERVED0; /*!< Reserved, 0x68 */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
/**
* @brief DMA2D Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
__IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
__IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
__IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
__IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
__IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
__IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
__IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
__IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
__IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
__IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
__IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
__IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
__IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
__IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
__IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
__IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
} DMA2D_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACECR;
__IO uint32_t MACPFR;
__IO uint32_t MACWTR;
__IO uint32_t MACHT0R;
__IO uint32_t MACHT1R;
uint32_t RESERVED1[14];
__IO uint32_t MACVTR;
uint32_t RESERVED2;
__IO uint32_t MACVHTR;
uint32_t RESERVED3;
__IO uint32_t MACVIR;
__IO uint32_t MACIVIR;
uint32_t RESERVED4[2];
__IO uint32_t MACTFCR;
uint32_t RESERVED5[7];
__IO uint32_t MACRFCR;
uint32_t RESERVED6[7];
__IO uint32_t MACISR;
__IO uint32_t MACIER;
__IO uint32_t MACRXTXSR;
uint32_t RESERVED7;
__IO uint32_t MACPCSR;
__IO uint32_t MACRWKPFR;
uint32_t RESERVED8[2];
__IO uint32_t MACLCSR;
__IO uint32_t MACLTCR;
__IO uint32_t MACLETR;
__IO uint32_t MAC1USTCR;
uint32_t RESERVED9[12];
__IO uint32_t MACVR;
__IO uint32_t MACDR;
uint32_t RESERVED10;
__IO uint32_t MACHWF0R;
__IO uint32_t MACHWF1R;
__IO uint32_t MACHWF2R;
uint32_t RESERVED11[54];
__IO uint32_t MACMDIOAR;
__IO uint32_t MACMDIODR;
uint32_t RESERVED12[2];
__IO uint32_t MACARPAR;
uint32_t RESERVED13[59];
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR;
uint32_t RESERVED14[248];
__IO uint32_t MMCCR;
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR;
uint32_t RESERVED15[14];
__IO uint32_t MMCTSCGPR;
__IO uint32_t MMCTMCGPR;
int32_t RESERVED16[5];
__IO uint32_t MMCTPCGR;
uint32_t RESERVED17[10];
__IO uint32_t MMCRCRCEPR;
__IO uint32_t MMCRAEPR;
uint32_t RESERVED18[10];
__IO uint32_t MMCRUPGR;
uint32_t RESERVED19[9];
__IO uint32_t MMCTLPIMSTR;
__IO uint32_t MMCTLPITCR;
__IO uint32_t MMCRLPIMSTR;
__IO uint32_t MMCRLPITCR;
uint32_t RESERVED20[65];
__IO uint32_t MACL3L4C0R;
__IO uint32_t MACL4A0R;
uint32_t RESERVED21[2];
__IO uint32_t MACL3A0R0R;
__IO uint32_t MACL3A1R0R;
__IO uint32_t MACL3A2R0R;
__IO uint32_t MACL3A3R0R;
uint32_t RESERVED22[4];
__IO uint32_t MACL3L4C1R;
__IO uint32_t MACL4A1R;
uint32_t RESERVED23[2];
__IO uint32_t MACL3A0R1R;
__IO uint32_t MACL3A1R1R;
__IO uint32_t MACL3A2R1R;
__IO uint32_t MACL3A3R1R;
uint32_t RESERVED24[108];
__IO uint32_t MACTSCR;
__IO uint32_t MACSSIR;
__IO uint32_t MACSTSR;
__IO uint32_t MACSTNR;
__IO uint32_t MACSTSUR;
__IO uint32_t MACSTNUR;
__IO uint32_t MACTSAR;
uint32_t RESERVED25;
__IO uint32_t MACTSSR;
uint32_t RESERVED26[3];
__IO uint32_t MACTTSSNR;
__IO uint32_t MACTTSSSR;
uint32_t RESERVED27[2];
__IO uint32_t MACACR;
uint32_t RESERVED28;
__IO uint32_t MACATSNR;
__IO uint32_t MACATSSR;
__IO uint32_t MACTSIACR;
__IO uint32_t MACTSEACR;
__IO uint32_t MACTSICNR;
__IO uint32_t MACTSECNR;
uint32_t RESERVED29[4];
__IO uint32_t MACPPSCR;
uint32_t RESERVED30[3];
__IO uint32_t MACPPSTTSR;
__IO uint32_t MACPPSTTNR;
__IO uint32_t MACPPSIR;
__IO uint32_t MACPPSWR;
uint32_t RESERVED31[12];
__IO uint32_t MACPOCR;
__IO uint32_t MACSPI0R;
__IO uint32_t MACSPI1R;
__IO uint32_t MACSPI2R;
__IO uint32_t MACLMIR;
uint32_t RESERVED32[11];
__IO uint32_t MTLOMR;
uint32_t RESERVED33[7];
__IO uint32_t MTLISR;
uint32_t RESERVED34[55];
__IO uint32_t MTLTQOMR;
__IO uint32_t MTLTQUR;
__IO uint32_t MTLTQDR;
uint32_t RESERVED35[8];
__IO uint32_t MTLQICSR;
__IO uint32_t MTLRQOMR;
__IO uint32_t MTLRQMPOCR;
__IO uint32_t MTLRQDR;
uint32_t RESERVED36[177];
__IO uint32_t DMAMR;
__IO uint32_t DMASBMR;
__IO uint32_t DMAISR;
__IO uint32_t DMADSR;
uint32_t RESERVED37[60];
__IO uint32_t DMACCR;
__IO uint32_t DMACTCR;
__IO uint32_t DMACRCR;
uint32_t RESERVED38[2];
__IO uint32_t DMACTDLAR;
uint32_t RESERVED39;
__IO uint32_t DMACRDLAR;
__IO uint32_t DMACTDTPR;
uint32_t RESERVED40;
__IO uint32_t DMACRDTPR;
__IO uint32_t DMACTDRLR;
__IO uint32_t DMACRDRLR;
__IO uint32_t DMACIER;
__IO uint32_t DMACRIWTR;
__IO uint32_t DMACSFCSR;
uint32_t RESERVED41;
__IO uint32_t DMACCATDR;
uint32_t RESERVED42;
__IO uint32_t DMACCARDR;
uint32_t RESERVED43;
__IO uint32_t DMACCATBR;
uint32_t RESERVED44;
__IO uint32_t DMACCARBR;
__IO uint32_t DMACSR;
uint32_t RESERVED45[2];
__IO uint32_t DMACMFCR;
}ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, Address offset: 0x0C */
__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x10 */
__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, Address offset: 0x2C */
__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x30 */
__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved, 0x38 */
uint32_t RESERVED4; /*!< Reserved, 0x3C */
__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, Address offset: 0x4C */
__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x50 */
__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x54 */
}EXTI_TypeDef;
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
uint32_t RESERVED1; /*!< Reserved, 0x0C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
}EXTI_Core_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
__IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
__IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
__IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
__IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
__IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */
__IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
__IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
__IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
__IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
__IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */
__IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
__IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
__IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
__IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
__IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
__IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
__IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
__IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
__IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
__IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
uint32_t RESERVED2; /*!< Reserved, 0x108 */
__IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
__IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
__IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
__IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
__IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
__IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
__IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
__IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
__IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
__IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
__IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
__IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
__IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
__IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
} FLASH_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank2
*/
typedef struct
{
__IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
__IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
__IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
__IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
uint32_t RESERVED0; /*!< Reserved, 0x70 */
__IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
} FMC_Bank2_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
uint32_t RESERVED; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief Flexible Memory Controller Bank5 and 6
*/
typedef struct
{
__IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
__IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
__IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
__IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
__IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
} FMC_Bank5_6_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
} OPAMP_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
__IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
__IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
__IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
__IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
__IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
__IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
__IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
__IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
__IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
__IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
__IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
__IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
__IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
__IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
__IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
__IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
__IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
__IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
__IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
__IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
__IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
__IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
__IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief JPEG Codec
*/
typedef struct
{
__IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
__IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
__IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
__IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
__IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
__IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
__IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
__IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
__IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
__IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
__IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
__IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
__IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
__IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
__IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
__IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
__IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
__IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
__IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
__IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
__IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
__IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
__IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
__IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
__IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
} JPEG_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
__IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
__IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
__IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
__IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
__IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
__IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
__IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
__IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
__IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
__IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
__IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
__IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
__IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
__IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
__IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
__IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
__IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
__IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
__IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
__IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
__IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
__IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
__IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
__IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
__IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
__IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
__IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA4 */
__IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
uint32_t RESERVED8[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
__IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
__IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
__IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
__IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
__IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
__IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0xF8 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
__IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
__IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
__IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
__IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
__IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
uint32_t RESERVED10[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
uint32_t reserved; /*!< Reserved */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAMPCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
__IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
__IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
__IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
__IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
__IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
__IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
__IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
__IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
__IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
__IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
__IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
__IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief SPDIF-RX Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
__IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
__IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
__IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
__IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1A */
} SPDIFRX_TypeDef;
/**
* @brief Secure digital input/output Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
__IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
__IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
__IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
__IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
} SDMMC_TypeDef;
/**
* @brief Delay Block DLYB
*/
typedef struct
{
__IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
} DLYB_TypeDef;
/**
* @brief HW Semaphore HSEM
*/
typedef struct
{
__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
__IO uint32_t IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
__IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
__IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
__IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch*/
__IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
__IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
} HSEM_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
__IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
__IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
__IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
__IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
__IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
__IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
__IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
__IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
__IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
__IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
} SPI_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
uint16_t RESERVED13; /*!< Reserved, 0x4E */
uint16_t RESERVED14; /*!< Reserved, 0x50 */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
} TIM_TypeDef;
/**
* @brief LPTIMIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
uint16_t RESERVED1; /*!< Reserved, 0x20 */
__IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
} LPTIM_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
__IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
__IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
} COMPOPT_TypeDef;
typedef struct
{
__IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
} COMP_Common_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
uint16_t RESERVED2; /*!< Reserved, 0x12 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
uint16_t RESERVED3; /*!< Reserved, 0x1A */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED4; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Single Wire Protocol Master Interface SPWMI
*/
typedef struct
{
__IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
__IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
uint32_t RESERVED1; /*!< Reserved, 0x08 */
__IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
__IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
__IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
__IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
__IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
__IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
__IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
} SWPMI_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief Crypto Processor
*/
typedef struct
{
__IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
__IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
__IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
__IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
__IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
__IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
__IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
__IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
__IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
__IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
__IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
__IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
__IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
__IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
__IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
__IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
__IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
__IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
__IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
__IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
__IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
__IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
__IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
__IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
__IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
__IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
__IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
__IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
__IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
__IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
__IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
} CRYP_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
} HASH_TypeDef;
/**
* @brief HASH_DIGEST
*/
typedef struct
{
__IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
} HASH_DIGEST_TypeDef;
/**
* @brief High resolution Timer (HRTIM)
*/
/* HRTIM master registers definition */
typedef struct
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
__IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
__IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
__IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
uint32_t RESERVED0; /*!< Reserved, 0x20 */
__IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
__IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
__IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
}HRTIM_Master_TypeDef;
/* HRTIM Timer A to E registers definition */
typedef struct
{
__IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
__IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
__IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
__IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
__IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
__IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
__IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
__IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
__IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
__IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
__IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
__IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
__IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
__IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
__IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
__IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
__IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
__IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
__IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
__IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
__IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
__IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
__IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
__IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
__IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
__IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
}HRTIM_Timerx_TypeDef;
/* HRTIM common register definition */
typedef struct
{
__IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
__IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
__IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
__IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
__IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
__IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
__IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
__IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
__IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
__IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
__IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
__IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
__IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
__IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
__IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
__IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
__IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
__IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
__IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
__IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
}HRTIM_Common_TypeDef;
/* HRTIM register definition */
typedef struct {
HRTIM_Master_TypeDef sMasterRegs;
HRTIM_Timerx_TypeDef sTimerxRegs[5];
uint32_t RESERVED0[32];
HRTIM_Common_TypeDef sCommonRegs;
}HRTIM_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief MDIOS
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t WRFR;
__IO uint32_t CWRFR;
__IO uint32_t RDFR;
__IO uint32_t CRDFR;
__IO uint32_t SR;
__IO uint32_t CLRFR;
uint32_t RESERVED[57];
__IO uint32_t DINR0;
__IO uint32_t DINR1;
__IO uint32_t DINR2;
__IO uint32_t DINR3;
__IO uint32_t DINR4;
__IO uint32_t DINR5;
__IO uint32_t DINR6;
__IO uint32_t DINR7;
__IO uint32_t DINR8;
__IO uint32_t DINR9;
__IO uint32_t DINR10;
__IO uint32_t DINR11;
__IO uint32_t DINR12;
__IO uint32_t DINR13;
__IO uint32_t DINR14;
__IO uint32_t DINR15;
__IO uint32_t DINR16;
__IO uint32_t DINR17;
__IO uint32_t DINR18;
__IO uint32_t DINR19;
__IO uint32_t DINR20;
__IO uint32_t DINR21;
__IO uint32_t DINR22;
__IO uint32_t DINR23;
__IO uint32_t DINR24;
__IO uint32_t DINR25;
__IO uint32_t DINR26;
__IO uint32_t DINR27;
__IO uint32_t DINR28;
__IO uint32_t DINR29;
__IO uint32_t DINR30;
__IO uint32_t DINR31;
__IO uint32_t DOUTR0;
__IO uint32_t DOUTR1;
__IO uint32_t DOUTR2;
__IO uint32_t DOUTR3;
__IO uint32_t DOUTR4;
__IO uint32_t DOUTR5;
__IO uint32_t DOUTR6;
__IO uint32_t DOUTR7;
__IO uint32_t DOUTR8;
__IO uint32_t DOUTR9;
__IO uint32_t DOUTR10;
__IO uint32_t DOUTR11;
__IO uint32_t DOUTR12;
__IO uint32_t DOUTR13;
__IO uint32_t DOUTR14;
__IO uint32_t DOUTR15;
__IO uint32_t DOUTR16;
__IO uint32_t DOUTR17;
__IO uint32_t DOUTR18;
__IO uint32_t DOUTR19;
__IO uint32_t DOUTR20;
__IO uint32_t DOUTR21;
__IO uint32_t DOUTR22;
__IO uint32_t DOUTR23;
__IO uint32_t DOUTR24;
__IO uint32_t DOUTR25;
__IO uint32_t DOUTR26;
__IO uint32_t DOUTR27;
__IO uint32_t DOUTR28;
__IO uint32_t DOUTR29;
__IO uint32_t DOUTR30;
__IO uint32_t DOUTR31;
} MDIOS_TypeDef;
/**
* @brief USB_OTG_Core_Registers
*/
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */
__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
__IO uint32_t GPWRDN; /*!< Power Down Register 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
} USB_OTG_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
__IO uint32_t DCTL; /*!< dev Control Register 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved9; /*!< Reserved 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
uint32_t Reserved40; /*!< dedicated EP mask 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
uint32_t Reserved[2]; /*!< Reserved */
} USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define D1_ITCMRAM_BASE ((uint32_t)0x00000000) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
#define D1_ITCMICP_BASE ((uint32_t)0x00100000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
#define D1_DTCMRAM_BASE ((uint32_t)0x20000000) /*!< Base address of : 128KB system data RAM accessible over DTCM */
#define D1_AXIFLASH_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
#define D1_AXIICP_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
#define D1_AXISRAM_BASE ((uint32_t)0x24000000) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
#define D2_AXISRAM_BASE ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
#define D2_AHBSRAM_BASE ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
#define D3_BKPSRAM_BASE ((uint32_t)0x38800000) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
/* Legacy define */
#define FLASH_BASE FLASH_BANK1_BASE
/*!< Peripheral memory map */
#define D2_APB1PERIPH_BASE PERIPH_BASE
#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000)
#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000)
#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000)
#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000)
#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000)
/*!< Legacy Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
/*!< D1_AHB1PERIPH peripherals */
#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000)
#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000)
#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000)
#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000)
#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000)
#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000)
#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000)
#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000)
#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000)
/*!< D2_AHB1PERIPH peripherals */
#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000)
#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400)
#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800)
#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000)
#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100)
#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300)
#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400)
#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (ETH_BASE)
/*!< USB registers base address */
#define USB1_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
#define USB2_OTG_FS_PERIPH_BASE ((uint32_t )0x40080000)
#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
#define USB_OTG_HOST_BASE ((uint32_t )0x400)
#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
/*!< D2_AHB2PERIPH peripherals */
#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000)
#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000)
#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400)
#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710)
#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800)
#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400)
#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800)
/*!< D3_AHB1PERIPH peripherals */
#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400)
#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800)
#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00)
#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000)
#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400)
#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800)
#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00)
#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000)
#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400)
#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800)
#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400)
#define RCC_C1_BASE (RCC_BASE + 0x130)
#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800)
#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00)
#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400)
#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800)
#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000)
#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300)
#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400)
/*!< D1_APB1PERIPH peripherals */
#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000)
/*!< D2_APB1PERIPH peripherals */
#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000)
#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400)
#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00)
#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000)
#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800)
#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00)
#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00)
#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400)
#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800)
#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00)
#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400)
#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800)
#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000)
#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000)
#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010)
#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400)
#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000)
#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400)
#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800)
#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00)
/*!< D2_APB2PERIPH peripherals */
#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000)
#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400)
#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000)
#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400)
#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000)
#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400)
#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000)
#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400)
#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800)
#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000)
#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000)
#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400)
#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
/*!< D3_APB1PERIPH peripherals */
#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000)
#define EXTI_D1_BASE (EXTI_BASE + 0x0080)
#define EXTI_D2_BASE (EXTI_BASE + 0x00C0)
#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400)
#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00)
#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400)
#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00)
#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400)
#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800)
#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00)
#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000)
#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800)
#define COMP1_BASE (COMP12_BASE + 0x0C)
#define COMP2_BASE (COMP12_BASE + 0x10)
#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00)
#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000)
#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800)
#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400)
#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008)
#define BDMA_Channel1_BASE (BDMA_BASE + 0x001C)
#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030)
#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044)
#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058)
#define BDMA_Channel5_BASE (BDMA_BASE + 0x006C)
#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080)
#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094)
#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004)
#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008)
#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000C)
#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010)
#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014)
#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018)
#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001C)
#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100)
#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104)
#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108)
#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010C)
#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110)
#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114)
#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118)
#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011C)
#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080)
#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110)
#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114)
#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118)
#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011C)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0x5C001000)
#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define HASH ((HASH_TypeDef *) HASH_BASE)
#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
#define ETH ((ETH_TypeDef *)ETH_BASE)
#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
/* Legacy defines */
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD_Pos (0U)
#define ADC_ISR_ADRD_Msk (0x1U << ADC_ISR_ADRD_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRD ADC_ISR_ADRD_Msk /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_RDY_Pos (0U)
#define ADC_IER_RDY_Msk (0x1U << ADC_IER_RDY_Pos) /*!< 0x00000001 */
#define ADC_IER_RDY ADC_IER_RDY_Msk /*!< ADC Ready (ADRDY) interrupt source */
#define ADC_IER_EOSMP_Pos (1U)
#define ADC_IER_EOSMP_Msk (0x1U << ADC_IER_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMP ADC_IER_EOSMP_Msk /*!< ADC End of Sampling interrupt source */
#define ADC_IER_EOC_Pos (2U)
#define ADC_IER_EOC_Msk (0x1U << ADC_IER_EOC_Pos) /*!< 0x00000004 */
#define ADC_IER_EOC ADC_IER_EOC_Msk /*!< ADC End of Regular Conversion interrupt source */
#define ADC_IER_EOS_Pos (3U)
#define ADC_IER_EOS_Msk (0x1U << ADC_IER_EOS_Pos) /*!< 0x00000008 */
#define ADC_IER_EOS ADC_IER_EOS_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
#define ADC_IER_OVR_Pos (4U)
#define ADC_IER_OVR_Msk (0x1U << ADC_IER_OVR_Pos) /*!< 0x00000010 */
#define ADC_IER_OVR ADC_IER_OVR_Msk /*!< ADC overrun interrupt source */
#define ADC_IER_JEOC_Pos (5U)
#define ADC_IER_JEOC_Msk (0x1U << ADC_IER_JEOC_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOC ADC_IER_JEOC_Msk /*!< ADC End of Injected Conversion interrupt source */
#define ADC_IER_JEOS_Pos (6U)
#define ADC_IER_JEOS_Msk (0x1U << ADC_IER_JEOS_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOS ADC_IER_JEOS_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
#define ADC_IER_AWD1_Pos (7U)
#define ADC_IER_AWD1_Msk (0x1U << ADC_IER_AWD1_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1 ADC_IER_AWD1_Msk /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IER_AWD2_Pos (8U)
#define ADC_IER_AWD2_Msk (0x1U << ADC_IER_AWD2_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2 ADC_IER_AWD2_Msk /*!< ADC Analog watchdog 2 interrupt source */
#define ADC_IER_AWD3_Pos (9U)
#define ADC_IER_AWD3_Msk (0x1U << ADC_IER_AWD3_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3 ADC_IER_AWD3_Msk /*!< ADC Analog watchdog 3 interrupt source */
#define ADC_IER_JQOVF_Pos (10U)
#define ADC_IER_JQOVF_Msk (0x1U << ADC_IER_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVF ADC_IER_JQOVF_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Boost Mode */
#define ADC_CR_BOOST_Pos (8U)
#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Stop of injected conversion */
#define ADC_CR_ADCALLIN_Pos (16U)
#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
#define ADC_CR_LINCALRDYW1_Pos (22U)
#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
#define ADC_CR_LINCALRDYW2_Pos (23U)
#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
#define ADC_CR_LINCALRDYW3_Pos (24U)
#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
#define ADC_CR_LINCALRDYW4_Pos (25U)
#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
#define ADC_CR_LINCALRDYW5_Pos (26U)
#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
#define ADC_CR_LINCALRDYW6_Pos (27U)
#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
/******************** Bit definition for ADC_CFGR register ********************/
#define ADC_CFGR_DMNGT_Pos (0U)
#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
#define ADC_CFGR_RES_Pos (2U)
#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
#define ADC_CFGR2_RSHIFT1_Pos (11U)
#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
#define ADC_CFGR2_RSHIFT2_Pos (12U)
#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
#define ADC_CFGR2_RSHIFT3_Pos (13U)
#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
#define ADC_CFGR2_RSHIFT4_Pos (14U)
#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
#define ADC_CFGR2_OSR_Pos (16U)
#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_LSHIFT_Pos (28U)
#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_SMPR1 register ********************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_SMPR2 register ********************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
#define ADC_SMPR2_SMP19_Pos (27U)
#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_PCSEL register ********************/
#define ADC_PCSEL_PCSEL_Pos (0U)
#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_LTR1 register ********************/
#define ADC_LTR1_LT1_Pos (0U)
#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_HTR1 register ********************/
#define ADC_HTR1_HT1_Pos (0U)
#define ADC_HTR1_HT1_Msk (0x3FFFFFFU << ADC_HTR1_HT1_Pos) /*!< 0x03FFFFFF */
#define ADC_HTR1_HT1 ADC_HTR1_HT1_Msk /*!< ADC Analog watchdog 1 higher threshold */
#define ADC_HTR1_HT1_0 (0x0000001U << ADC_HTR1_HT1_Pos) /*!< 0x00000001 */
#define ADC_HTR1_HT1_1 (0x0000002U << ADC_HTR1_HT1_Pos) /*!< 0x00000002 */
#define ADC_HTR1_HT1_2 (0x0000004U << ADC_HTR1_HT1_Pos) /*!< 0x00000004 */
#define ADC_HTR1_HT1_3 (0x0000008U << ADC_HTR1_HT1_Pos) /*!< 0x00000008 */
#define ADC_HTR1_HT1_4 (0x0000010U << ADC_HTR1_HT1_Pos) /*!< 0x00000010 */
#define ADC_HTR1_HT1_5 (0x0000020U << ADC_HTR1_HT1_Pos) /*!< 0x00000020 */
#define ADC_HTR1_HT1_6 (0x0000040U << ADC_HTR1_HT1_Pos) /*!< 0x00000040 */
#define ADC_HTR1_HT1_7 (0x0000080U << ADC_HTR1_HT1_Pos) /*!< 0x00000080 */
#define ADC_HTR1_HT1_8 (0x0000100U << ADC_HTR1_HT1_Pos) /*!< 0x00000100 */
#define ADC_HTR1_HT1_9 (0x0000200U << ADC_HTR1_HT1_Pos) /*!< 0x00000200 */
#define ADC_HTR1_HT1_10 (0x0000400U << ADC_HTR1_HT1_Pos) /*!< 0x00000400 */
#define ADC_HTR1_HT1_11 (0x0000800U << ADC_HTR1_HT1_Pos) /*!< 0x00000800 */
#define ADC_HTR1_HT1_12 (0x0001000U << ADC_HTR1_HT1_Pos) /*!< 0x00001000 */
#define ADC_HTR1_HT1_13 (0x0002000U << ADC_HTR1_HT1_Pos) /*!< 0x00002000 */
#define ADC_HTR1_HT1_14 (0x0004000U << ADC_HTR1_HT1_Pos) /*!< 0x00004000 */
#define ADC_HTR1_HT1_15 (0x0008000U << ADC_HTR1_HT1_Pos) /*!< 0x00008000 */
#define ADC_HTR1_HT1_16 (0x0010000U << ADC_HTR1_HT1_Pos) /*!< 0x00010000 */
#define ADC_HTR1_HT1_17 (0x0020000U << ADC_HTR1_HT1_Pos) /*!< 0x00020000 */
#define ADC_HTR1_HT1_18 (0x0040000U << ADC_HTR1_HT1_Pos) /*!< 0x00040000 */
#define ADC_HTR1_HT1_19 (0x0080000U << ADC_HTR1_HT1_Pos) /*!< 0x00080000 */
#define ADC_HTR1_HT1_20 (0x0100000U << ADC_HTR1_HT1_Pos) /*!< 0x00100000 */
#define ADC_HTR1_HT1_21 (0x0200000U << ADC_HTR1_HT1_Pos) /*!< 0x00200000 */
#define ADC_HTR1_HT1_22 (0x0400000U << ADC_HTR1_HT1_Pos) /*!< 0x00400000 */
#define ADC_HTR1_HT1_23 (0x0800000U << ADC_HTR1_HT1_Pos) /*!< 0x00800000 */
#define ADC_HTR1_HT1_24 (0x1000000U << ADC_HTR1_HT1_Pos) /*!< 0x01000000 */
#define ADC_HTR1_HT1_25 (0x2000000U << ADC_HTR1_HT1_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_LTR2 register ********************/
#define ADC_LTR2_LT2_Pos (0U)
#define ADC_LTR2_LT2_Msk (0x3FFFFFFU << ADC_LTR2_LT2_Pos) /*!< 0x03FFFFFF */
#define ADC_LTR2_LT2 ADC_LTR2_LT2_Msk /*!< ADC Analog watchdog 2 lower threshold */
#define ADC_LTR2_LT2_0 (0x0000001U << ADC_LTR2_LT2_Pos) /*!< 0x00000001 */
#define ADC_LTR2_LT2_1 (0x0000002U << ADC_LTR2_LT2_Pos) /*!< 0x00000002 */
#define ADC_LTR2_LT2_2 (0x0000004U << ADC_LTR2_LT2_Pos) /*!< 0x00000004 */
#define ADC_LTR2_LT2_3 (0x0000008U << ADC_LTR2_LT2_Pos) /*!< 0x00000008 */
#define ADC_LTR2_LT2_4 (0x0000010U << ADC_LTR2_LT2_Pos) /*!< 0x00000010 */
#define ADC_LTR2_LT2_5 (0x0000020U << ADC_LTR2_LT2_Pos) /*!< 0x00000020 */
#define ADC_LTR2_LT2_6 (0x0000040U << ADC_LTR2_LT2_Pos) /*!< 0x00000040 */
#define ADC_LTR2_LT2_7 (0x0000080U << ADC_LTR2_LT2_Pos) /*!< 0x00000080 */
#define ADC_LTR2_LT2_8 (0x0000100U << ADC_LTR2_LT2_Pos) /*!< 0x00000100 */
#define ADC_LTR2_LT2_9 (0x0000200U << ADC_LTR2_LT2_Pos) /*!< 0x00000200 */
#define ADC_LTR2_LT2_10 (0x0000400U << ADC_LTR2_LT2_Pos) /*!< 0x00000400 */
#define ADC_LTR2_LT2_11 (0x0000800U << ADC_LTR2_LT2_Pos) /*!< 0x00000800 */
#define ADC_LTR2_LT2_12 (0x0001000U << ADC_LTR2_LT2_Pos) /*!< 0x00001000 */
#define ADC_LTR2_LT2_13 (0x0002000U << ADC_LTR2_LT2_Pos) /*!< 0x00002000 */
#define ADC_LTR2_LT2_14 (0x0004000U << ADC_LTR2_LT2_Pos) /*!< 0x00004000 */
#define ADC_LTR2_LT2_15 (0x0008000U << ADC_LTR2_LT2_Pos) /*!< 0x00008000 */
#define ADC_LTR2_LT2_16 (0x0010000U << ADC_LTR2_LT2_Pos) /*!< 0x00010000 */
#define ADC_LTR2_LT2_17 (0x0020000U << ADC_LTR2_LT2_Pos) /*!< 0x00020000 */
#define ADC_LTR2_LT2_18 (0x0040000U << ADC_LTR2_LT2_Pos) /*!< 0x00040000 */
#define ADC_LTR2_LT2_19 (0x0080000U << ADC_LTR2_LT2_Pos) /*!< 0x00080000 */
#define ADC_LTR2_LT2_20 (0x0100000U << ADC_LTR2_LT2_Pos) /*!< 0x00100000 */
#define ADC_LTR2_LT2_21 (0x0200000U << ADC_LTR2_LT2_Pos) /*!< 0x00200000 */
#define ADC_LTR2_LT2_22 (0x0400000U << ADC_LTR2_LT2_Pos) /*!< 0x00400000 */
#define ADC_LTR2_LT2_23 (0x0800000U << ADC_LTR2_LT2_Pos) /*!< 0x00800000 */
#define ADC_LTR2_LT2_24 (0x1000000U << ADC_LTR2_LT2_Pos) /*!< 0x01000000 */
#define ADC_LTR2_LT2_25 (0x2000000U << ADC_LTR2_LT2_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_HTR2 register ********************/
#define ADC_HTR2_HT2_Pos (0U)
#define ADC_HTR2_HT2_Msk (0x3FFFFFFU << ADC_HTR2_HT2_Pos) /*!< 0x03FFFFFF */
#define ADC_HTR2_HT2 ADC_HTR2_HT2_Msk /*!< ADC Analog watchdog 2 higher threshold */
#define ADC_HTR2_HT2_0 (0x0000001U << ADC_HTR2_HT2_Pos) /*!< 0x00000001 */
#define ADC_HTR2_HT2_1 (0x0000002U << ADC_HTR2_HT2_Pos) /*!< 0x00000002 */
#define ADC_HTR2_HT2_2 (0x0000004U << ADC_HTR2_HT2_Pos) /*!< 0x00000004 */
#define ADC_HTR2_HT2_3 (0x0000008U << ADC_HTR2_HT2_Pos) /*!< 0x00000008 */
#define ADC_HTR2_HT2_4 (0x0000010U << ADC_HTR2_HT2_Pos) /*!< 0x00000010 */
#define ADC_HTR2_HT2_5 (0x0000020U << ADC_HTR2_HT2_Pos) /*!< 0x00000020 */
#define ADC_HTR2_HT2_6 (0x0000040U << ADC_HTR2_HT2_Pos) /*!< 0x00000040 */
#define ADC_HTR2_HT2_7 (0x0000080U << ADC_HTR2_HT2_Pos) /*!< 0x00000080 */
#define ADC_HTR2_HT2_8 (0x0000100U << ADC_HTR2_HT2_Pos) /*!< 0x00000100 */
#define ADC_HTR2_HT2_9 (0x0000200U << ADC_HTR2_HT2_Pos) /*!< 0x00000200 */
#define ADC_HTR2_HT2_10 (0x0000400U << ADC_HTR2_HT2_Pos) /*!< 0x00000400 */
#define ADC_HTR2_HT2_11 (0x0000800U << ADC_HTR2_HT2_Pos) /*!< 0x00000800 */
#define ADC_HTR2_HT2_12 (0x0001000U << ADC_HTR2_HT2_Pos) /*!< 0x00001000 */
#define ADC_HTR2_HT2_13 (0x0002000U << ADC_HTR2_HT2_Pos) /*!< 0x00002000 */
#define ADC_HTR2_HT2_14 (0x0004000U << ADC_HTR2_HT2_Pos) /*!< 0x00004000 */
#define ADC_HTR2_HT2_15 (0x0008000U << ADC_HTR2_HT2_Pos) /*!< 0x00008000 */
#define ADC_HTR2_HT2_16 (0x0010000U << ADC_HTR2_HT2_Pos) /*!< 0x00010000 */
#define ADC_HTR2_HT2_17 (0x0020000U << ADC_HTR2_HT2_Pos) /*!< 0x00020000 */
#define ADC_HTR2_HT2_18 (0x0040000U << ADC_HTR2_HT2_Pos) /*!< 0x00040000 */
#define ADC_HTR2_HT2_19 (0x0080000U << ADC_HTR2_HT2_Pos) /*!< 0x00080000 */
#define ADC_HTR2_HT2_20 (0x0100000U << ADC_HTR2_HT2_Pos) /*!< 0x00100000 */
#define ADC_HTR2_HT2_21 (0x0200000U << ADC_HTR2_HT2_Pos) /*!< 0x00200000 */
#define ADC_HTR2_HT2_22 (0x0400000U << ADC_HTR2_HT2_Pos) /*!< 0x00400000 */
#define ADC_HTR2_HT2_23 (0x0800000U << ADC_HTR2_HT2_Pos) /*!< 0x00800000 */
#define ADC_HTR2_HT2_24 (0x1000000U << ADC_HTR2_HT2_Pos) /*!< 0x01000000 */
#define ADC_HTR2_HT2_25 (0x2000000U << ADC_HTR2_HT2_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_LTR3 register ********************/
#define ADC_LTR3_LT3_Pos (0U)
#define ADC_LTR3_LT3_Msk (0x3FFFFFFU << ADC_LTR3_LT3_Pos) /*!< 0x03FFFFFF */
#define ADC_LTR3_LT3 ADC_LTR3_LT3_Msk /*!< ADC Analog watchdog 3 lower threshold */
#define ADC_LTR3_LT3_0 (0x0000001U << ADC_LTR3_LT3_Pos) /*!< 0x00000001 */
#define ADC_LTR3_LT3_1 (0x0000002U << ADC_LTR3_LT3_Pos) /*!< 0x00000002 */
#define ADC_LTR3_LT3_2 (0x0000004U << ADC_LTR3_LT3_Pos) /*!< 0x00000004 */
#define ADC_LTR3_LT3_3 (0x0000008U << ADC_LTR3_LT3_Pos) /*!< 0x00000008 */
#define ADC_LTR3_LT3_4 (0x0000010U << ADC_LTR3_LT3_Pos) /*!< 0x00000010 */
#define ADC_LTR3_LT3_5 (0x0000020U << ADC_LTR3_LT3_Pos) /*!< 0x00000020 */
#define ADC_LTR3_LT3_6 (0x0000040U << ADC_LTR3_LT3_Pos) /*!< 0x00000040 */
#define ADC_LTR3_LT3_7 (0x0000080U << ADC_LTR3_LT3_Pos) /*!< 0x00000080 */
#define ADC_LTR3_LT3_8 (0x0000100U << ADC_LTR3_LT3_Pos) /*!< 0x00000100 */
#define ADC_LTR3_LT3_9 (0x0000200U << ADC_LTR3_LT3_Pos) /*!< 0x00000200 */
#define ADC_LTR3_LT3_10 (0x0000400U << ADC_LTR3_LT3_Pos) /*!< 0x00000400 */
#define ADC_LTR3_LT3_11 (0x0000800U << ADC_LTR3_LT3_Pos) /*!< 0x00000800 */
#define ADC_LTR3_LT3_12 (0x0001000U << ADC_LTR3_LT3_Pos) /*!< 0x00001000 */
#define ADC_LTR3_LT3_13 (0x0002000U << ADC_LTR3_LT3_Pos) /*!< 0x00002000 */
#define ADC_LTR3_LT3_14 (0x0004000U << ADC_LTR3_LT3_Pos) /*!< 0x00004000 */
#define ADC_LTR3_LT3_15 (0x0008000U << ADC_LTR3_LT3_Pos) /*!< 0x00008000 */
#define ADC_LTR3_LT3_16 (0x0010000U << ADC_LTR3_LT3_Pos) /*!< 0x00010000 */
#define ADC_LTR3_LT3_17 (0x0020000U << ADC_LTR3_LT3_Pos) /*!< 0x00020000 */
#define ADC_LTR3_LT3_18 (0x0040000U << ADC_LTR3_LT3_Pos) /*!< 0x00040000 */
#define ADC_LTR3_LT3_19 (0x0080000U << ADC_LTR3_LT3_Pos) /*!< 0x00080000 */
#define ADC_LTR3_LT3_20 (0x0100000U << ADC_LTR3_LT3_Pos) /*!< 0x00100000 */
#define ADC_LTR3_LT3_21 (0x0200000U << ADC_LTR3_LT3_Pos) /*!< 0x00200000 */
#define ADC_LTR3_LT3_22 (0x0400000U << ADC_LTR3_LT3_Pos) /*!< 0x00400000 */
#define ADC_LTR3_LT3_23 (0x0800000U << ADC_LTR3_LT3_Pos) /*!< 0x00800000 */
#define ADC_LTR3_LT3_24 (0x1000000U << ADC_LTR3_LT3_Pos) /*!< 0x01000000 */
#define ADC_LTR3_LT3_25 (0x2000000U << ADC_LTR3_LT3_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_HTR3 register ********************/
#define ADC_HTR3_HT3_Pos (0U)
#define ADC_HTR3_HT3_Msk (0x3FFFFFFU << ADC_HTR3_HT3_Pos) /*!< 0x03FFFFFF */
#define ADC_HTR3_HT3 ADC_HTR3_HT3_Msk /*!< ADC Analog watchdog 3 higher threshold */
#define ADC_HTR3_HT3_0 (0x0000001U << ADC_HTR3_HT3_Pos) /*!< 0x00000001 */
#define ADC_HTR3_HT3_1 (0x0000002U << ADC_HTR3_HT3_Pos) /*!< 0x00000002 */
#define ADC_HTR3_HT3_2 (0x0000004U << ADC_HTR3_HT3_Pos) /*!< 0x00000004 */
#define ADC_HTR3_HT3_3 (0x0000008U << ADC_HTR3_HT3_Pos) /*!< 0x00000008 */
#define ADC_HTR3_HT3_4 (0x0000010U << ADC_HTR3_HT3_Pos) /*!< 0x00000010 */
#define ADC_HTR3_HT3_5 (0x0000020U << ADC_HTR3_HT3_Pos) /*!< 0x00000020 */
#define ADC_HTR3_HT3_6 (0x0000040U << ADC_HTR3_HT3_Pos) /*!< 0x00000040 */
#define ADC_HTR3_HT3_7 (0x0000080U << ADC_HTR3_HT3_Pos) /*!< 0x00000080 */
#define ADC_HTR3_HT3_8 (0x0000100U << ADC_HTR3_HT3_Pos) /*!< 0x00000100 */
#define ADC_HTR3_HT3_9 (0x0000200U << ADC_HTR3_HT3_Pos) /*!< 0x00000200 */
#define ADC_HTR3_HT3_10 (0x0000400U << ADC_HTR3_HT3_Pos) /*!< 0x00000400 */
#define ADC_HTR3_HT3_11 (0x0000800U << ADC_HTR3_HT3_Pos) /*!< 0x00000800 */
#define ADC_HTR3_HT3_12 (0x0001000U << ADC_HTR3_HT3_Pos) /*!< 0x00001000 */
#define ADC_HTR3_HT3_13 (0x0002000U << ADC_HTR3_HT3_Pos) /*!< 0x00002000 */
#define ADC_HTR3_HT3_14 (0x0004000U << ADC_HTR3_HT3_Pos) /*!< 0x00004000 */
#define ADC_HTR3_HT3_15 (0x0008000U << ADC_HTR3_HT3_Pos) /*!< 0x00008000 */
#define ADC_HTR3_HT3_16 (0x0010000U << ADC_HTR3_HT3_Pos) /*!< 0x00010000 */
#define ADC_HTR3_HT3_17 (0x0020000U << ADC_HTR3_HT3_Pos) /*!< 0x00020000 */
#define ADC_HTR3_HT3_18 (0x0040000U << ADC_HTR3_HT3_Pos) /*!< 0x00040000 */
#define ADC_HTR3_HT3_19 (0x0080000U << ADC_HTR3_HT3_Pos) /*!< 0x00080000 */
#define ADC_HTR3_HT3_20 (0x0100000U << ADC_HTR3_HT3_Pos) /*!< 0x00100000 */
#define ADC_HTR3_HT3_21 (0x0200000U << ADC_HTR3_HT3_Pos) /*!< 0x00200000 */
#define ADC_HTR3_HT3_22 (0x0400000U << ADC_HTR3_HT3_Pos) /*!< 0x00400000 */
#define ADC_HTR3_HT3_23 (0x0800000U << ADC_HTR3_HT3_Pos) /*!< 0x00800000 */
#define ADC_HTR3_HT3_24 (0x1000000U << ADC_HTR3_HT3_Pos) /*!< 0x01000000 */
#define ADC_HTR3_HT3_25 (0x2000000U << ADC_HTR3_HT3_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ********************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ********************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ********************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
#define ADC_DR_RDATA_0 (0x00000001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x00000002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
#define ADC_DR_RDATA_2 (0x00000004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
#define ADC_DR_RDATA_3 (0x00000008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
#define ADC_DR_RDATA_4 (0x00000010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
#define ADC_DR_RDATA_5 (0x00000020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
#define ADC_DR_RDATA_6 (0x00000040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
#define ADC_DR_RDATA_7 (0x00000080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
#define ADC_DR_RDATA_8 (0x00000100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
#define ADC_DR_RDATA_9 (0x00000200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
#define ADC_DR_RDATA_10 (0x00000400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
#define ADC_DR_RDATA_11 (0x00000800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
#define ADC_DR_RDATA_12 (0x00001000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
#define ADC_DR_RDATA_13 (0x00002000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
#define ADC_DR_RDATA_14 (0x00004000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
#define ADC_DR_RDATA_15 (0x00008000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
#define ADC_DR_RDATA_16 (0x00010000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
#define ADC_DR_RDATA_17 (0x00020000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
#define ADC_DR_RDATA_18 (0x00040000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
#define ADC_DR_RDATA_19 (0x00080000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
#define ADC_DR_RDATA_20 (0x00100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
#define ADC_DR_RDATA_21 (0x00200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
#define ADC_DR_RDATA_22 (0x00400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
#define ADC_DR_RDATA_23 (0x00800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
#define ADC_DR_RDATA_24 (0x01000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
#define ADC_DR_RDATA_25 (0x02000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
#define ADC_DR_RDATA_26 (0x04000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
#define ADC_DR_RDATA_27 (0x08000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JSQR register ********************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ********************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_SSATE_Pos (31U)
#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR2 register ********************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_SSATE_Pos (31U)
#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR3 register ********************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_SSATE_Pos (31U)
#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR4 register ********************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_SSATE_Pos (31U)
#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_JDR1 register ********************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR1_JDATA_0 (0x00000001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x00000002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2 (0x00000004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3 (0x00000008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4 (0x00000010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5 (0x00000020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6 (0x00000040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7 (0x00000080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8 (0x00000100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9 (0x00000200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10 (0x00000400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11 (0x00000800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12 (0x00001000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13 (0x00002000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14 (0x00004000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15 (0x00008000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR1_JDATA_16 (0x00010000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR1_JDATA_17 (0x00020000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR1_JDATA_18 (0x00040000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR1_JDATA_19 (0x00080000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR1_JDATA_20 (0x00100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR1_JDATA_21 (0x00200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR1_JDATA_22 (0x00400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR1_JDATA_23 (0x00800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR1_JDATA_24 (0x01000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR1_JDATA_25 (0x02000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR1_JDATA_26 (0x04000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR1_JDATA_27 (0x08000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR2 register ********************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR2_JDATA_0 (0x00000001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x00000002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2 (0x00000004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3 (0x00000008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4 (0x00000010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5 (0x00000020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6 (0x00000040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7 (0x00000080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8 (0x00000100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9 (0x00000200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10 (0x00000400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11 (0x00000800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12 (0x00001000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13 (0x00002000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14 (0x00004000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15 (0x00008000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR2_JDATA_16 (0x00010000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR2_JDATA_17 (0x00020000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR2_JDATA_18 (0x00040000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR2_JDATA_19 (0x00080000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR2_JDATA_20 (0x00100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR2_JDATA_21 (0x00200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR2_JDATA_22 (0x00400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR2_JDATA_23 (0x00800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR2_JDATA_24 (0x01000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR2_JDATA_25 (0x02000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR2_JDATA_26 (0x04000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR2_JDATA_27 (0x08000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR3 register ********************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR3_JDATA_0 (0x00000001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x00000002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2 (0x00000004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3 (0x00000008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4 (0x00000010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5 (0x00000020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6 (0x00000040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7 (0x00000080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8 (0x00000100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9 (0x00000200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10 (0x00000400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11 (0x00000800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12 (0x00001000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13 (0x00002000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14 (0x00004000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15 (0x00008000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR3_JDATA_16 (0x00010000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR3_JDATA_17 (0x00020000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR3_JDATA_18 (0x00040000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR3_JDATA_19 (0x00080000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR3_JDATA_20 (0x00100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR3_JDATA_21 (0x00200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR3_JDATA_22 (0x00400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR3_JDATA_23 (0x00800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR3_JDATA_24 (0x01000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR3_JDATA_25 (0x02000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR3_JDATA_26 (0x04000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR3_JDATA_27 (0x08000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR4 register ********************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR4_JDATA_0 (0x00000001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x00000002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2 (0x00000004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3 (0x00000008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4 (0x00000010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5 (0x00000020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6 (0x00000040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7 (0x00000080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8 (0x00000100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9 (0x00000200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10 (0x00000400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11 (0x00000800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12 (0x00001000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13 (0x00002000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14 (0x00004000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15 (0x00008000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR4_JDATA_16 (0x00010000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR4_JDATA_17 (0x00020000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR4_JDATA_18 (0x00040000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR4_JDATA_19 (0x00080000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR4_JDATA_20 (0x00100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR4_JDATA_21 (0x00200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR4_JDATA_22 (0x00400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR4_JDATA_23 (0x00800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR4_JDATA_24 (0x01000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR4_JDATA_25 (0x02000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR4_JDATA_26 (0x04000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR4_JDATA_27 (0x08000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_AWD2CR register ********************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_AWD3CR register ********************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_DIFSEL register ********************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_CALFACT register ********************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_CALFACT2 register ********************/
#define ADC_CALFACT2_LINCALFACT_Pos (0U)
#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
#define ADC_CALFACT2_LINCALFACT_27 (0x08000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register ********************/
#define ADC123_CSR_ADRDY_MST_Pos (0U)
#define ADC123_CSR_ADRDY_MST_Msk (0x1U << ADC123_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC123_CSR_ADRDY_MST ADC123_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
#define ADC123_CSR_EOSMP_MST_Pos (1U)
#define ADC123_CSR_EOSMP_MST_Msk (0x1U << ADC123_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC123_CSR_EOSMP_MST ADC123_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
#define ADC123_CSR_EOC_MST_Pos (2U)
#define ADC123_CSR_EOC_MST_Msk (0x1U << ADC123_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC123_CSR_EOC_MST ADC123_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
#define ADC123_CSR_EOS_MST_Pos (3U)
#define ADC123_CSR_EOS_MST_Msk (0x1U << ADC123_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC123_CSR_EOS_MST ADC123_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
#define ADC123_CSR_OVR_MST_Pos (4U)
#define ADC123_CSR_OVR_MST_Msk (0x1U << ADC123_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC123_CSR_OVR_MST ADC123_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
#define ADC123_CSR_JEOC_MST_Pos (5U)
#define ADC123_CSR_JEOC_MST_Msk (0x1U << ADC123_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC123_CSR_JEOC_MST ADC123_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
#define ADC123_CSR_JEOS_MST_Pos (6U)
#define ADC123_CSR_JEOS_MST_Msk (0x1U << ADC123_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC123_CSR_JEOS_MST ADC123_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
#define ADC123_CSR_AWD1_MST_Pos (7U)
#define ADC123_CSR_AWD1_MST_Msk (0x1U << ADC123_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC123_CSR_AWD1_MST ADC123_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
#define ADC123_CSR_AWD2_MST_Pos (8U)
#define ADC123_CSR_AWD2_MST_Msk (0x1U << ADC123_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC123_CSR_AWD2_MST ADC123_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
#define ADC123_CSR_AWD3_MST_Pos (9U)
#define ADC123_CSR_AWD3_MST_Msk (0x1U << ADC123_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC123_CSR_AWD3_MST ADC123_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
#define ADC123_CSR_JQOVF_MST_Pos (10U)
#define ADC123_CSR_JQOVF_MST_Msk (0x1U << ADC123_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC123_CSR_JQOVF_MST ADC123_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
#define ADC123_CSR_ADRDY_SLV_Pos (16U)
#define ADC123_CSR_ADRDY_SLV_Msk (0x1U << ADC123_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC123_CSR_ADRDY_SLV ADC123_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
#define ADC123_CSR_EOSMP_SLV_Pos (17U)
#define ADC123_CSR_EOSMP_SLV_Msk (0x1U << ADC123_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC123_CSR_EOSMP_SLV ADC123_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
#define ADC123_CSR_EOC_SLV_Pos (18U)
#define ADC123_CSR_EOC_SLV_Msk (0x1U << ADC123_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC123_CSR_EOC_SLV ADC123_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
#define ADC123_CSR_EOS_SLV_Pos (19U)
#define ADC123_CSR_EOS_SLV_Msk (0x1U << ADC123_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC123_CSR_EOS_SLV ADC123_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC123_CSR_OVR_SLV_Pos (20U)
#define ADC123_CSR_OVR_SLV_Msk (0x1U << ADC123_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC123_CSR_OVR_SLV ADC123_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC123_CSR_JEOC_SLV_Pos (21U)
#define ADC123_CSR_JEOC_SLV_Msk (0x1U << ADC123_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC123_CSR_JEOC_SLV ADC123_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
#define ADC123_CSR_JEOS_SLV_Pos (22U)
#define ADC123_CSR_JEOS_SLV_Msk (0x1U << ADC123_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC123_CSR_JEOS_SLV ADC123_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
#define ADC123_CSR_AWD1_SLV_Pos (23U)
#define ADC123_CSR_AWD1_SLV_Msk (0x1U << ADC123_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC123_CSR_AWD1_SLV ADC123_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
#define ADC123_CSR_AWD2_SLV_Pos (24U)
#define ADC123_CSR_AWD2_SLV_Msk (0x1U << ADC123_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC123_CSR_AWD2_SLV ADC123_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
#define ADC123_CSR_AWD3_SLV_Pos (25U)
#define ADC123_CSR_AWD3_SLV_Msk (0x1U << ADC123_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC123_CSR_AWD3_SLV ADC123_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
#define ADC123_CSR_JQOVF_SLV_Pos (26U)
#define ADC123_CSR_JQOVF_SLV_Msk (0x1U << ADC123_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC123_CSR_JQOVF_SLV ADC123_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
/******************** Bit definition for ADC_CCR register ********************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DAMDF_Pos (14U)
#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
#define ADC_CCR_TSEN_Pos (23U)
#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
#define ADC_CCR_VBATEN_Pos (24U)
#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
/******************** Bit definition for ADC_CDR register ********************/
#define ADC123_CDR_RDATA_MST_Pos (0U)
#define ADC123_CDR_RDATA_MST_Msk (0xFFFFU << ADC123_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC123_CDR_RDATA_MST ADC123_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
#define ADC123_CDR_RDATA_MST_0 (0x0001U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
#define ADC123_CDR_RDATA_MST_1 (0x0002U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
#define ADC123_CDR_RDATA_MST_2 (0x0004U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
#define ADC123_CDR_RDATA_MST_3 (0x0008U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
#define ADC123_CDR_RDATA_MST_4 (0x0010U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
#define ADC123_CDR_RDATA_MST_5 (0x0020U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
#define ADC123_CDR_RDATA_MST_6 (0x0040U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
#define ADC123_CDR_RDATA_MST_7 (0x0080U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
#define ADC123_CDR_RDATA_MST_8 (0x0100U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
#define ADC123_CDR_RDATA_MST_9 (0x0200U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
#define ADC123_CDR_RDATA_MST_10 (0x0400U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
#define ADC123_CDR_RDATA_MST_11 (0x0800U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
#define ADC123_CDR_RDATA_MST_12 (0x1000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
#define ADC123_CDR_RDATA_MST_13 (0x2000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
#define ADC123_CDR_RDATA_MST_14 (0x4000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
#define ADC123_CDR_RDATA_MST_15 (0x8000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
#define ADC123_CDR_RDATA_SLV_Pos (16U)
#define ADC123_CDR_RDATA_SLV_Msk (0xFFFFU << ADC123_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC123_CDR_RDATA_SLV ADC123_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
#define ADC123_CDR_RDATA_SLV_0 (0x0001U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
#define ADC123_CDR_RDATA_SLV_1 (0x0002U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
#define ADC123_CDR_RDATA_SLV_2 (0x0004U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
#define ADC123_CDR_RDATA_SLV_3 (0x0008U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
#define ADC123_CDR_RDATA_SLV_4 (0x0010U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
#define ADC123_CDR_RDATA_SLV_5 (0x0020U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
#define ADC123_CDR_RDATA_SLV_6 (0x0040U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
#define ADC123_CDR_RDATA_SLV_7 (0x0080U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
#define ADC123_CDR_RDATA_SLV_8 (0x0100U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
#define ADC123_CDR_RDATA_SLV_9 (0x0200U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
#define ADC123_CDR_RDATA_SLV_10 (0x0400U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
#define ADC123_CDR_RDATA_SLV_11 (0x0800U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
#define ADC123_CDR_RDATA_SLV_12 (0x1000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
#define ADC123_CDR_RDATA_SLV_13 (0x2000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
#define ADC123_CDR_RDATA_SLV_14 (0x4000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
#define ADC123_CDR_RDATA_SLV_15 (0x8000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_CDR2 register ********************/
#define ADC123_CDR2_RDATA_ALT_Pos (0U)
#define ADC123_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC123_CDR2_RDATA_ALT ADC123_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
#define ADC123_CDR2_RDATA_ALT_0 (0x00000001U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
#define ADC123_CDR2_RDATA_ALT_1 (0x00000002U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
#define ADC123_CDR2_RDATA_ALT_2 (0x00000004U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
#define ADC123_CDR2_RDATA_ALT_3 (0x00000008U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
#define ADC123_CDR2_RDATA_ALT_4 (0x00000010U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
#define ADC123_CDR2_RDATA_ALT_5 (0x00000020U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
#define ADC123_CDR2_RDATA_ALT_6 (0x00000040U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
#define ADC123_CDR2_RDATA_ALT_7 (0x00000080U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
#define ADC123_CDR2_RDATA_ALT_8 (0x00000100U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
#define ADC123_CDR2_RDATA_ALT_9 (0x00000200U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
#define ADC123_CDR2_RDATA_ALT_10 (0x00000400U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
#define ADC123_CDR2_RDATA_ALT_11 (0x00000800U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
#define ADC123_CDR2_RDATA_ALT_12 (0x00001000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
#define ADC123_CDR2_RDATA_ALT_13 (0x00002000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
#define ADC123_CDR2_RDATA_ALT_14 (0x00004000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
#define ADC123_CDR2_RDATA_ALT_15 (0x00008000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
#define ADC123_CDR2_RDATA_ALT_16 (0x00010000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
#define ADC123_CDR2_RDATA_ALT_17 (0x00020000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
#define ADC123_CDR2_RDATA_ALT_18 (0x00040000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
#define ADC123_CDR2_RDATA_ALT_19 (0x00080000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
#define ADC123_CDR2_RDATA_ALT_20 (0x00100000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
#define ADC123_CDR2_RDATA_ALT_21 (0x00200000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
#define ADC123_CDR2_RDATA_ALT_22 (0x00400000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
#define ADC123_CDR2_RDATA_ALT_23 (0x00800000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
#define ADC123_CDR2_RDATA_ALT_24 (0x01000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
#define ADC123_CDR2_RDATA_ALT_25 (0x02000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
#define ADC123_CDR2_RDATA_ALT_26 (0x04000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
#define ADC123_CDR2_RDATA_ALT_27 (0x08000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
#define ADC123_CDR2_RDATA_ALT_28 (0x10000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
#define ADC123_CDR2_RDATA_ALT_29 (0x20000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
#define ADC123_CDR2_RDATA_ALT_30 (0x40000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
#define ADC123_CDR2_RDATA_ALT_31 (0x80000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x7U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1U << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
#define VREFBUF_CSR_VRS_OUT3_Msk (0x1U << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
#define VREFBUF_CSR_VRS_OUT4_Msk (0x3U << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
/******************* Bit definition for VREFBUF_CCR register ****************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFU << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFU << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFU << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFU << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFU << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFU << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFU << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFU << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFU << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0xFU << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00000F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FU << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1U << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1U << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3U << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1U << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFU << FDCAN_RWD_WDC_Pos) /*!< 0x0000000F */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (4U)
#define FDCAN_RWD_WDV_Msk (0xFU << FDCAN_RWD_WDV_Pos) /*!< 0x000000F0 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1U << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1U << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1U << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1U << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1U << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1U << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1U << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1U << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1U << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1U << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1U << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1U << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1U << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1U << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_TSEG2_Pos (0U)
#define FDCAN_NBTP_TSEG2_Msk (0x7FU << FDCAN_NBTP_TSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_TSEG2 FDCAN_NBTP_TSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFU << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFU << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FU << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3U << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFU << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFU << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1U << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3U << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFU << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFU << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFU << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_TREC_Pos (8U)
#define FDCAN_ECR_TREC_Msk (0x7FU << FDCAN_ECR_TREC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_TREC FDCAN_ECR_TREC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1U << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFU << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7U << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3U << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1U << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1U << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1U << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7U << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1U << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1U << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1U << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1U << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FU << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FU << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FU << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1U << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0W_Pos (1U)
#define FDCAN_IR_RF0W_Msk (0x1U << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
#define FDCAN_IR_RF0F_Pos (2U)
#define FDCAN_IR_RF0F_Msk (0x1U << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (3U)
#define FDCAN_IR_RF0L_Msk (0x1U << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (4U)
#define FDCAN_IR_RF1N_Msk (0x1U << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1W_Pos (5U)
#define FDCAN_IR_RF1W_Msk (0x1U << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
#define FDCAN_IR_RF1F_Pos (6U)
#define FDCAN_IR_RF1F_Msk (0x1U << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (7U)
#define FDCAN_IR_RF1L_Msk (0x1U << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (8U)
#define FDCAN_IR_HPM_Msk (0x1U << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (9U)
#define FDCAN_IR_TC_Msk (0x1U << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (10U)
#define FDCAN_IR_TCF_Msk (0x1U << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (11U)
#define FDCAN_IR_TFE_Msk (0x1U << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (12U)
#define FDCAN_IR_TEFN_Msk (0x1U << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFW_Pos (13U)
#define FDCAN_IR_TEFW_Msk (0x1U << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
#define FDCAN_IR_TEFF_Pos (14U)
#define FDCAN_IR_TEFF_Msk (0x1U << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (15U)
#define FDCAN_IR_TEFL_Msk (0x1U << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (16U)
#define FDCAN_IR_TSW_Msk (0x1U << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (17U)
#define FDCAN_IR_MRAF_Msk (0x1U << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (18U)
#define FDCAN_IR_TOO_Msk (0x1U << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_DRX_Pos (19U)
#define FDCAN_IR_DRX_Msk (0x1U << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
#define FDCAN_IR_ELO_Pos (22U)
#define FDCAN_IR_ELO_Msk (0x1U << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (23U)
#define FDCAN_IR_EP_Msk (0x1U << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (24U)
#define FDCAN_IR_EW_Msk (0x1U << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (25U)
#define FDCAN_IR_BO_Msk (0x1U << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (26U)
#define FDCAN_IR_WDI_Msk (0x1U << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (27U)
#define FDCAN_IR_PEA_Msk (0x1U << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (28U)
#define FDCAN_IR_PED_Msk (0x1U << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (29U)
#define FDCAN_IR_ARA_Msk (0x1U << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1U << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0WE_Pos (1U)
#define FDCAN_IE_RF0WE_Msk (0x1U << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
#define FDCAN_IE_RF0FE_Pos (2U)
#define FDCAN_IE_RF0FE_Msk (0x1U << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (3U)
#define FDCAN_IE_RF0LE_Msk (0x1U << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (4U)
#define FDCAN_IE_RF1NE_Msk (0x1U << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1WE_Pos (5U)
#define FDCAN_IE_RF1WE_Msk (0x1U << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
#define FDCAN_IE_RF1FE_Pos (6U)
#define FDCAN_IE_RF1FE_Msk (0x1U << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (7U)
#define FDCAN_IE_RF1LE_Msk (0x1U << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (8U)
#define FDCAN_IE_HPME_Msk (0x1U << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (9U)
#define FDCAN_IE_TCE_Msk (0x1U << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (10U)
#define FDCAN_IE_TCFE_Msk (0x1U << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
#define FDCAN_IE_TFEE_Pos (11U)
#define FDCAN_IE_TFEE_Msk (0x1U << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (12U)
#define FDCAN_IE_TEFNE_Msk (0x1U << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFWE_Pos (13U)
#define FDCAN_IE_TEFWE_Msk (0x1U << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
#define FDCAN_IE_TEFFE_Pos (14U)
#define FDCAN_IE_TEFFE_Msk (0x1U << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (15U)
#define FDCAN_IE_TEFLE_Msk (0x1U << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (16U)
#define FDCAN_IE_TSWE_Msk (0x1U << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (17U)
#define FDCAN_IE_MRAFE_Msk (0x1U << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (18U)
#define FDCAN_IE_TOOE_Msk (0x1U << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_DRXE_Pos (19U)
#define FDCAN_IE_DRXE_Msk (0x1U << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
#define FDCAN_IE_BECE_Pos (20U)
#define FDCAN_IE_BECE_Msk (0x1U << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
#define FDCAN_IE_BEUE_Pos (21U)
#define FDCAN_IE_BEUE_Msk (0x1U << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
#define FDCAN_IE_ELOE_Pos (22U)
#define FDCAN_IE_ELOE_Msk (0x1U << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (23U)
#define FDCAN_IE_EPE_Msk (0x1U << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (24U)
#define FDCAN_IE_EWE_Msk (0x1U << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (25U)
#define FDCAN_IE_BOE_Msk (0x1U << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (26U)
#define FDCAN_IE_WDIE_Msk (0x1U << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (27U)
#define FDCAN_IE_PEAE_Msk (0x1U << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
#define FDCAN_IE_PEDE_Pos (28U)
#define FDCAN_IE_PEDE_Msk (0x1U << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (29U)
#define FDCAN_IE_ARAE_Msk (0x1U << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RF0NL_Pos (0U)
#define FDCAN_ILS_RF0NL_Msk (0x1U << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
#define FDCAN_ILS_RF0WL_Pos (1U)
#define FDCAN_ILS_RF0WL_Msk (0x1U << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
#define FDCAN_ILS_RF0FL_Pos (2U)
#define FDCAN_ILS_RF0FL_Msk (0x1U << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
#define FDCAN_ILS_RF0LL_Pos (3U)
#define FDCAN_ILS_RF0LL_Msk (0x1U << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
#define FDCAN_ILS_RF1NL_Pos (4U)
#define FDCAN_ILS_RF1NL_Msk (0x1U << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
#define FDCAN_ILS_RF1WL_Pos (5U)
#define FDCAN_ILS_RF1WL_Msk (0x1U << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
#define FDCAN_ILS_RF1FL_Pos (6U)
#define FDCAN_ILS_RF1FL_Msk (0x1U << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
#define FDCAN_ILS_RF1LL_Pos (7U)
#define FDCAN_ILS_RF1LL_Msk (0x1U << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
#define FDCAN_ILS_HPML_Pos (8U)
#define FDCAN_ILS_HPML_Msk (0x1U << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
#define FDCAN_ILS_TCL_Pos (9U)
#define FDCAN_ILS_TCL_Msk (0x1U << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
#define FDCAN_ILS_TCFL_Pos (10U)
#define FDCAN_ILS_TCFL_Msk (0x1U << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
#define FDCAN_ILS_TFEL_Pos (11U)
#define FDCAN_ILS_TFEL_Msk (0x1U << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
#define FDCAN_ILS_TEFNL_Pos (12U)
#define FDCAN_ILS_TEFNL_Msk (0x1U << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
#define FDCAN_ILS_TEFWL_Pos (13U)
#define FDCAN_ILS_TEFWL_Msk (0x1U << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
#define FDCAN_ILS_TEFFL_Pos (14U)
#define FDCAN_ILS_TEFFL_Msk (0x1U << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
#define FDCAN_ILS_TEFLL_Pos (15U)
#define FDCAN_ILS_TEFLL_Msk (0x1U << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
#define FDCAN_ILS_TSWL_Pos (16U)
#define FDCAN_ILS_TSWL_Msk (0x1U << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
#define FDCAN_ILS_MRAFE_Pos (17U)
#define FDCAN_ILS_MRAFE_Msk (0x1U << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
#define FDCAN_ILS_TOOE_Pos (18U)
#define FDCAN_ILS_TOOE_Msk (0x1U << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
#define FDCAN_ILS_DRXE_Pos (19U)
#define FDCAN_ILS_DRXE_Msk (0x1U << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
#define FDCAN_ILS_BECE_Pos (20U)
#define FDCAN_ILS_BECE_Msk (0x1U << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
#define FDCAN_ILS_BEUE_Pos (21U)
#define FDCAN_ILS_BEUE_Msk (0x1U << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
#define FDCAN_ILS_ELOE_Pos (22U)
#define FDCAN_ILS_ELOE_Msk (0x1U << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
#define FDCAN_ILS_EPE_Pos (23U)
#define FDCAN_ILS_EPE_Msk (0x1U << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
#define FDCAN_ILS_EWE_Pos (24U)
#define FDCAN_ILS_EWE_Msk (0x1U << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
#define FDCAN_ILS_BOE_Pos (25U)
#define FDCAN_ILS_BOE_Msk (0x1U << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
#define FDCAN_ILS_WDIE_Pos (26U)
#define FDCAN_ILS_WDIE_Msk (0x1U << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
#define FDCAN_ILS_PEAE_Pos (27U)
#define FDCAN_ILS_PEAE_Msk (0x1U << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
#define FDCAN_ILS_PEDE_Pos (28U)
#define FDCAN_ILS_PEDE_Msk (0x1U << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
#define FDCAN_ILS_ARAE_Pos (29U)
#define FDCAN_ILS_ARAE_Msk (0x1U << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1U << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1U << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_GFC register **********************/
#define FDCAN_GFC_RRFE_Pos (0U)
#define FDCAN_GFC_RRFE_Msk (0x1U << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_GFC_RRFS_Pos (1U)
#define FDCAN_GFC_RRFS_Msk (0x1U << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_GFC_ANFE_Pos (2U)
#define FDCAN_GFC_ANFE_Msk (0x3U << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_GFC_ANFS_Pos (4U)
#define FDCAN_GFC_ANFS_Msk (0x3U << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
/***************** Bit definition for FDCAN_SIDFC register ********************/
#define FDCAN_SIDFC_FLSSA_Pos (2U)
#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFU << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_SIDFC_LSS_Pos (16U)
#define FDCAN_SIDFC_LSS_Msk (0xFFU << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
/***************** Bit definition for FDCAN_XIDFC register ********************/
#define FDCAN_XIDFC_FLESA_Pos (2U)
#define FDCAN_XIDFC_FLESA_Msk (0x3FFFU << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_XIDFC_LSE_Pos (16U)
#define FDCAN_XIDFC_LSE_Msk (0xFFU << FDCAN_XIDFC_LSE_Pos) /*!< 0x00FF0000 */
#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFU << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x3FU << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3U << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x7FU << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1U << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_NDAT1 register ********************/
#define FDCAN_NDAT1_ND0_Pos (0U)
#define FDCAN_NDAT1_ND0_Msk (0x1U << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
#define FDCAN_NDAT1_ND1_Pos (1U)
#define FDCAN_NDAT1_ND1_Msk (0x1U << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
#define FDCAN_NDAT1_ND2_Pos (2U)
#define FDCAN_NDAT1_ND2_Msk (0x1U << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
#define FDCAN_NDAT1_ND3_Pos (3U)
#define FDCAN_NDAT1_ND3_Msk (0x1U << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
#define FDCAN_NDAT1_ND4_Pos (4U)
#define FDCAN_NDAT1_ND4_Msk (0x1U << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
#define FDCAN_NDAT1_ND5_Pos (5U)
#define FDCAN_NDAT1_ND5_Msk (0x1U << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
#define FDCAN_NDAT1_ND6_Pos (6U)
#define FDCAN_NDAT1_ND6_Msk (0x1U << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
#define FDCAN_NDAT1_ND7_Pos (7U)
#define FDCAN_NDAT1_ND7_Msk (0x1U << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
#define FDCAN_NDAT1_ND8_Pos (8U)
#define FDCAN_NDAT1_ND8_Msk (0x1U << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
#define FDCAN_NDAT1_ND9_Pos (9U)
#define FDCAN_NDAT1_ND9_Msk (0x1U << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
#define FDCAN_NDAT1_ND10_Pos (10U)
#define FDCAN_NDAT1_ND10_Msk (0x1U << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
#define FDCAN_NDAT1_ND11_Pos (11U)
#define FDCAN_NDAT1_ND11_Msk (0x1U << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
#define FDCAN_NDAT1_ND12_Pos (12U)
#define FDCAN_NDAT1_ND12_Msk (0x1U << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
#define FDCAN_NDAT1_ND13_Pos (13U)
#define FDCAN_NDAT1_ND13_Msk (0x1U << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
#define FDCAN_NDAT1_ND14_Pos (14U)
#define FDCAN_NDAT1_ND14_Msk (0x1U << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
#define FDCAN_NDAT1_ND15_Pos (15U)
#define FDCAN_NDAT1_ND15_Msk (0x1U << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
#define FDCAN_NDAT1_ND16_Pos (16U)
#define FDCAN_NDAT1_ND16_Msk (0x1U << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
#define FDCAN_NDAT1_ND17_Pos (17U)
#define FDCAN_NDAT1_ND17_Msk (0x1U << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
#define FDCAN_NDAT1_ND18_Pos (18U)
#define FDCAN_NDAT1_ND18_Msk (0x1U << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
#define FDCAN_NDAT1_ND19_Pos (19U)
#define FDCAN_NDAT1_ND19_Msk (0x1U << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
#define FDCAN_NDAT1_ND20_Pos (20U)
#define FDCAN_NDAT1_ND20_Msk (0x1U << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
#define FDCAN_NDAT1_ND21_Pos (21U)
#define FDCAN_NDAT1_ND21_Msk (0x1U << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
#define FDCAN_NDAT1_ND22_Pos (22U)
#define FDCAN_NDAT1_ND22_Msk (0x1U << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
#define FDCAN_NDAT1_ND23_Pos (23U)
#define FDCAN_NDAT1_ND23_Msk (0x1U << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
#define FDCAN_NDAT1_ND24_Pos (24U)
#define FDCAN_NDAT1_ND24_Msk (0x1U << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
#define FDCAN_NDAT1_ND25_Pos (25U)
#define FDCAN_NDAT1_ND25_Msk (0x1U << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
#define FDCAN_NDAT1_ND26_Pos (26U)
#define FDCAN_NDAT1_ND26_Msk (0x1U << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
#define FDCAN_NDAT1_ND27_Pos (27U)
#define FDCAN_NDAT1_ND27_Msk (0x1U << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
#define FDCAN_NDAT1_ND28_Pos (28U)
#define FDCAN_NDAT1_ND28_Msk (0x1U << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
#define FDCAN_NDAT1_ND29_Pos (29U)
#define FDCAN_NDAT1_ND29_Msk (0x1U << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
#define FDCAN_NDAT1_ND30_Pos (30U)
#define FDCAN_NDAT1_ND30_Msk (0x1U << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
#define FDCAN_NDAT1_ND31_Pos (31U)
#define FDCAN_NDAT1_ND31_Msk (0x1U << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
/***************** Bit definition for FDCAN_NDAT2 register ********************/
#define FDCAN_NDAT2_ND32_Pos (0U)
#define FDCAN_NDAT2_ND32_Msk (0x1U << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
#define FDCAN_NDAT2_ND33_Pos (1U)
#define FDCAN_NDAT2_ND33_Msk (0x1U << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
#define FDCAN_NDAT2_ND34_Pos (2U)
#define FDCAN_NDAT2_ND34_Msk (0x1U << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
#define FDCAN_NDAT2_ND35_Pos (3U)
#define FDCAN_NDAT2_ND35_Msk (0x1U << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
#define FDCAN_NDAT2_ND36_Pos (4U)
#define FDCAN_NDAT2_ND36_Msk (0x1U << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
#define FDCAN_NDAT2_ND37_Pos (5U)
#define FDCAN_NDAT2_ND37_Msk (0x1U << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
#define FDCAN_NDAT2_ND38_Pos (6U)
#define FDCAN_NDAT2_ND38_Msk (0x1U << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
#define FDCAN_NDAT2_ND39_Pos (7U)
#define FDCAN_NDAT2_ND39_Msk (0x1U << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
#define FDCAN_NDAT2_ND40_Pos (8U)
#define FDCAN_NDAT2_ND40_Msk (0x1U << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
#define FDCAN_NDAT2_ND41_Pos (9U)
#define FDCAN_NDAT2_ND41_Msk (0x1U << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
#define FDCAN_NDAT2_ND42_Pos (10U)
#define FDCAN_NDAT2_ND42_Msk (0x1U << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
#define FDCAN_NDAT2_ND43_Pos (11U)
#define FDCAN_NDAT2_ND43_Msk (0x1U << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
#define FDCAN_NDAT2_ND44_Pos (12U)
#define FDCAN_NDAT2_ND44_Msk (0x1U << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
#define FDCAN_NDAT2_ND45_Pos (13U)
#define FDCAN_NDAT2_ND45_Msk (0x1U << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
#define FDCAN_NDAT2_ND46_Pos (14U)
#define FDCAN_NDAT2_ND46_Msk (0x1U << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
#define FDCAN_NDAT2_ND47_Pos (15U)
#define FDCAN_NDAT2_ND47_Msk (0x1U << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
#define FDCAN_NDAT2_ND48_Pos (16U)
#define FDCAN_NDAT2_ND48_Msk (0x1U << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
#define FDCAN_NDAT2_ND49_Pos (17U)
#define FDCAN_NDAT2_ND49_Msk (0x1U << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
#define FDCAN_NDAT2_ND50_Pos (18U)
#define FDCAN_NDAT2_ND50_Msk (0x1U << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
#define FDCAN_NDAT2_ND51_Pos (19U)
#define FDCAN_NDAT2_ND51_Msk (0x1U << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
#define FDCAN_NDAT2_ND52_Pos (20U)
#define FDCAN_NDAT2_ND52_Msk (0x1U << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
#define FDCAN_NDAT2_ND53_Pos (21U)
#define FDCAN_NDAT2_ND53_Msk (0x1U << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
#define FDCAN_NDAT2_ND54_Pos (22U)
#define FDCAN_NDAT2_ND54_Msk (0x1U << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
#define FDCAN_NDAT2_ND55_Pos (23U)
#define FDCAN_NDAT2_ND55_Msk (0x1U << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
#define FDCAN_NDAT2_ND56_Pos (24U)
#define FDCAN_NDAT2_ND56_Msk (0x1U << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
#define FDCAN_NDAT2_ND57_Pos (25U)
#define FDCAN_NDAT2_ND57_Msk (0x1U << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
#define FDCAN_NDAT2_ND58_Pos (26U)
#define FDCAN_NDAT2_ND58_Msk (0x1U << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
#define FDCAN_NDAT2_ND59_Pos (27U)
#define FDCAN_NDAT2_ND59_Msk (0x1U << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
#define FDCAN_NDAT2_ND60_Pos (28U)
#define FDCAN_NDAT2_ND60_Msk (0x1U << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
#define FDCAN_NDAT2_ND61_Pos (29U)
#define FDCAN_NDAT2_ND61_Msk (0x1U << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
#define FDCAN_NDAT2_ND62_Pos (30U)
#define FDCAN_NDAT2_ND62_Msk (0x1U << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
#define FDCAN_NDAT2_ND63_Pos (31U)
#define FDCAN_NDAT2_ND63_Msk (0x1U << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
/***************** Bit definition for FDCAN_RXF0C register ********************/
#define FDCAN_RXF0C_F0SA_Pos (2U)
#define FDCAN_RXF0C_F0SA_Msk (0x3FFFU << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
#define FDCAN_RXF0C_F0S_Pos (16U)
#define FDCAN_RXF0C_F0S_Msk (0x7FU << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
#define FDCAN_RXF0C_F0WM_Pos (24U)
#define FDCAN_RXF0C_F0WM_Msk (0x7FU << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
#define FDCAN_RXF0C_F0OM_Pos (31U)
#define FDCAN_RXF0C_F0OM_Msk (0x1U << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0x7FU << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3FU << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3FU << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1U << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1U << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x3FU << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXBC register ********************/
#define FDCAN_RXBC_RBSA_Pos (2U)
#define FDCAN_RXBC_RBSA_Msk (0x3FU << FDCAN_RXBC_RBSA_Pos) /*!< 0x000000FC */
#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
/***************** Bit definition for FDCAN_RXF1C register ********************/
#define FDCAN_RXF1C_F1SA_Pos (2U)
#define FDCAN_RXF1C_F1SA_Msk (0x3FU << FDCAN_RXF1C_F1SA_Pos) /*!< 0x000000FC */
#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
#define FDCAN_RXF1C_F1S_Pos (16U)
#define FDCAN_RXF1C_F1S_Msk (0x7FU << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
#define FDCAN_RXF1C_F1WM_Pos (24U)
#define FDCAN_RXF1C_F1WM_Msk (0x7FU << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
#define FDCAN_RXF1C_F1OM_Pos (31U)
#define FDCAN_RXF1C_F1OM_Msk (0x1U << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0x7FU << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3FU << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3FU << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1U << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1U << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x3FU << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_RXESC register ********************/
#define FDCAN_RXESC_F0DS_Pos (0U)
#define FDCAN_RXESC_F0DS_Msk (0x7U << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
#define FDCAN_RXESC_F1DS_Pos (4U)
#define FDCAN_RXESC_F1DS_Msk (0x7U << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
#define FDCAN_RXESC_RBDS_Pos (8U)
#define FDCAN_RXESC_RBDS_Msk (0x7U << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TBSA_Pos (2U)
#define FDCAN_TXBC_TBSA_Msk (0x3FU << FDCAN_TXBC_TBSA_Pos) /*!< 0x000000FC */
#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
#define FDCAN_TXBC_NDTB_Pos (16U)
#define FDCAN_TXBC_NDTB_Msk (0x3FU << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
#define FDCAN_TXBC_TFQS_Pos (24U)
#define FDCAN_TXBC_TFQS_Msk (0x3FU << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
#define FDCAN_TXBC_TFQM_Pos (30U)
#define FDCAN_TXBC_TFQM_Msk (0x1U << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x3FU << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x1FU << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x1FU << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1U << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXESC register *********************/
#define FDCAN_TXESC_TBDS_Pos (0U)
#define FDCAN_TXESC_TBDS_Msk (0x7U << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFU << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFU << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFU << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFU << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFU << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CF_Pos (0U)
#define FDCAN_TXBCIE_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCIE_CF_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCIE_CF FDCAN_TXBCIE_CF_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFC register *********************/
#define FDCAN_TXEFC_EFSA_Pos (2U)
#define FDCAN_TXEFC_EFSA_Msk (0x3FU << FDCAN_TXEFC_EFSA_Pos) /*!< 0x000000FC */
#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
#define FDCAN_TXEFC_EFS_Pos (8U)
#define FDCAN_TXEFC_EFS_Msk (0x3FU << FDCAN_TXEFC_EFS_Pos) /*!< 0x00003F00 */
#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
#define FDCAN_TXEFC_EFWM_Pos (24U)
#define FDCAN_TXEFC_EFWM_Msk (0x3FU << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x3FU << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x1FU << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x1FU << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1U << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1U << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x1FU << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/***************** Bit definition for FDCAN_TTTMC register *********************/
#define FDCAN_TTTMC_TMSA_Pos (2U)
#define FDCAN_TTTMC_TMSA_Msk (0x3FFFU << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
#define FDCAN_TTTMC_TME_Pos (16U)
#define FDCAN_TTTMC_TME_Msk (0x7FU << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
/***************** Bit definition for FDCAN_TTRMC register *********************/
#define FDCAN_TTRMC_RID_Pos (0U)
#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFU << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
#define FDCAN_TTRMC_XTD_Pos (30U)
#define FDCAN_TTRMC_XTD_Msk (0x1U << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
#define FDCAN_TTRMC_RMPS_Pos (31U)
#define FDCAN_TTRMC_RMPS_Msk (0x1U << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
/***************** Bit definition for FDCAN_TTOCF register *********************/
#define FDCAN_TTOCF_OM_Pos (0U)
#define FDCAN_TTOCF_OM_Msk (0x3U << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
#define FDCAN_TTOCF_GEN_Pos (3U)
#define FDCAN_TTOCF_GEN_Msk (0x1U << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
#define FDCAN_TTOCF_TM_Pos (4U)
#define FDCAN_TTOCF_TM_Msk (0x1U << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
#define FDCAN_TTOCF_LDSDL_Pos (5U)
#define FDCAN_TTOCF_LDSDL_Msk (0x7U << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
#define FDCAN_TTOCF_IRTO_Pos (8U)
#define FDCAN_TTOCF_IRTO_Msk (0x7FU << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
#define FDCAN_TTOCF_EECS_Pos (15U)
#define FDCAN_TTOCF_EECS_Msk (0x1U << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
#define FDCAN_TTOCF_AWL_Pos (16U)
#define FDCAN_TTOCF_AWL_Msk (0xFFU << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
#define FDCAN_TTOCF_EGTF_Pos (24U)
#define FDCAN_TTOCF_EGTF_Msk (0x1U << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
#define FDCAN_TTOCF_ECC_Pos (25U)
#define FDCAN_TTOCF_ECC_Msk (0x1U << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
#define FDCAN_TTOCF_EVTP_Pos (26U)
#define FDCAN_TTOCF_EVTP_Msk (0x1U << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
/***************** Bit definition for FDCAN_TTMLM register *********************/
#define FDCAN_TTMLM_CCM_Pos (0U)
#define FDCAN_TTMLM_CCM_Msk (0x3FU << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
#define FDCAN_TTMLM_CSS_Pos (6U)
#define FDCAN_TTMLM_CSS_Msk (0x3U << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
#define FDCAN_TTMLM_TXEW_Pos (8U)
#define FDCAN_TTMLM_TXEW_Msk (0xFU << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
#define FDCAN_TTMLM_ENTT_Pos (16U)
#define FDCAN_TTMLM_ENTT_Msk (0xFFFU << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
/***************** Bit definition for FDCAN_TURCF register *********************/
#define FDCAN_TURCF_NCL_Pos (0U)
#define FDCAN_TURCF_NCL_Msk (0xFFFFU << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
#define FDCAN_TURCF_DC_Pos (16U)
#define FDCAN_TURCF_DC_Msk (0x3FFFU << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
#define FDCAN_TURCF_ELT_Pos (31U)
#define FDCAN_TURCF_ELT_Msk (0x1U << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
/***************** Bit definition for FDCAN_TTOCN register ********************/
#define FDCAN_TTOCN_SGT_Pos (0U)
#define FDCAN_TTOCN_SGT_Msk (0x1U << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
#define FDCAN_TTOCN_ECS_Pos (1U)
#define FDCAN_TTOCN_ECS_Msk (0x1U << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
#define FDCAN_TTOCN_SWP_Pos (2U)
#define FDCAN_TTOCN_SWP_Msk (0x1U << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
#define FDCAN_TTOCN_SWS_Pos (3U)
#define FDCAN_TTOCN_SWS_Msk (0x3U << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
#define FDCAN_TTOCN_RTIE_Pos (5U)
#define FDCAN_TTOCN_RTIE_Msk (0x1U << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_TMC_Pos (6U)
#define FDCAN_TTOCN_TMC_Msk (0x3U << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
#define FDCAN_TTOCN_TTIE_Pos (8U)
#define FDCAN_TTOCN_TTIE_Msk (0x1U << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_GCS_Pos (9U)
#define FDCAN_TTOCN_GCS_Msk (0x1U << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
#define FDCAN_TTOCN_FGP_Pos (10U)
#define FDCAN_TTOCN_FGP_Msk (0x1U << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
#define FDCAN_TTOCN_TMG_Pos (11U)
#define FDCAN_TTOCN_TMG_Msk (0x1U << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
#define FDCAN_TTOCN_NIG_Pos (12U)
#define FDCAN_TTOCN_NIG_Msk (0x1U << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
#define FDCAN_TTOCN_ESCN_Pos (13U)
#define FDCAN_TTOCN_ESCN_Msk (0x1U << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
#define FDCAN_TTOCN_LCKC_Pos (15U)
#define FDCAN_TTOCN_LCKC_Msk (0x1U << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
/***************** Bit definition for FDCAN_TTGTP register ********************/
#define FDCAN_TTGTP_TP_Pos (0U)
#define FDCAN_TTGTP_TP_Msk (0xFFFFU << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
#define FDCAN_TTGTP_CTP_Pos (16U)
#define FDCAN_TTGTP_CTP_Msk (0xFFFFU << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
/***************** Bit definition for FDCAN_TTTMK register ********************/
#define FDCAN_TTTMK_TM_Pos (0U)
#define FDCAN_TTTMK_TM_Msk (0xFFFFU << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
#define FDCAN_TTTMK_TICC_Pos (16U)
#define FDCAN_TTTMK_TICC_Msk (0x7FU << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
#define FDCAN_TTTMK_LCKM_Pos (31U)
#define FDCAN_TTTMK_LCKM_Msk (0x1U << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
/***************** Bit definition for FDCAN_TTIR register ********************/
#define FDCAN_TTIR_SBC_Pos (0U)
#define FDCAN_TTIR_SBC_Msk (0x1U << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
#define FDCAN_TTIR_SMC_Pos (1U)
#define FDCAN_TTIR_SMC_Msk (0x1U << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
#define FDCAN_TTIR_CSM_Pos (2U)
#define FDCAN_TTIR_CSM_Msk (0x1U << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
#define FDCAN_TTIR_SOG_Pos (3U)
#define FDCAN_TTIR_SOG_Msk (0x1U << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
#define FDCAN_TTIR_RTMI_Pos (4U)
#define FDCAN_TTIR_RTMI_Msk (0x1U << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
#define FDCAN_TTIR_TTMI_Pos (5U)
#define FDCAN_TTIR_TTMI_Msk (0x1U << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
#define FDCAN_TTIR_SWE_Pos (6U)
#define FDCAN_TTIR_SWE_Msk (0x1U << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
#define FDCAN_TTIR_GTW_Pos (7U)
#define FDCAN_TTIR_GTW_Msk (0x1U << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
#define FDCAN_TTIR_GTD_Pos (8U)
#define FDCAN_TTIR_GTD_Msk (0x1U << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
#define FDCAN_TTIR_GTE_Pos (9U)
#define FDCAN_TTIR_GTE_Msk (0x1U << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
#define FDCAN_TTIR_TXU_Pos (10U)
#define FDCAN_TTIR_TXU_Msk (0x1U << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
#define FDCAN_TTIR_TXO_Pos (11U)
#define FDCAN_TTIR_TXO_Msk (0x1U << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
#define FDCAN_TTIR_SE1_Pos (12U)
#define FDCAN_TTIR_SE1_Msk (0x1U << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
#define FDCAN_TTIR_SE2_Pos (13U)
#define FDCAN_TTIR_SE2_Msk (0x1U << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
#define FDCAN_TTIR_ELC_Pos (14U)
#define FDCAN_TTIR_ELC_Msk (0x1U << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
#define FDCAN_TTIR_IWT_Pos (15U)
#define FDCAN_TTIR_IWT_Msk (0x1U << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
#define FDCAN_TTIR_WT_Pos (16U)
#define FDCAN_TTIR_WT_Msk (0x1U << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
#define FDCAN_TTIR_AW_Pos (17U)
#define FDCAN_TTIR_AW_Msk (0x1U << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
#define FDCAN_TTIR_CER_Pos (18U)
#define FDCAN_TTIR_CER_Msk (0x1U << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
/***************** Bit definition for FDCAN_TTIE register ********************/
#define FDCAN_TTIE_SBCE_Pos (0U)
#define FDCAN_TTIE_SBCE_Msk (0x1U << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
#define FDCAN_TTIE_SMCE_Pos (1U)
#define FDCAN_TTIE_SMCE_Msk (0x1U << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
#define FDCAN_TTIE_CSME_Pos (2U)
#define FDCAN_TTIE_CSME_Msk (0x1U << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
#define FDCAN_TTIE_SOGE_Pos (3U)
#define FDCAN_TTIE_SOGE_Msk (0x1U << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
#define FDCAN_TTIE_RTMIE_Pos (4U)
#define FDCAN_TTIE_RTMIE_Msk (0x1U << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
#define FDCAN_TTIE_TTMIE_Pos (5U)
#define FDCAN_TTIE_TTMIE_Msk (0x1U << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
#define FDCAN_TTIE_SWEE_Pos (6U)
#define FDCAN_TTIE_SWEE_Msk (0x1U << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
#define FDCAN_TTIE_GTWE_Pos (7U)
#define FDCAN_TTIE_GTWE_Msk (0x1U << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
#define FDCAN_TTIE_GTDE_Pos (8U)
#define FDCAN_TTIE_GTDE_Msk (0x1U << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
#define FDCAN_TTIE_GTEE_Pos (9U)
#define FDCAN_TTIE_GTEE_Msk (0x1U << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
#define FDCAN_TTIE_TXUE_Pos (10U)
#define FDCAN_TTIE_TXUE_Msk (0x1U << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
#define FDCAN_TTIE_TXOE_Pos (11U)
#define FDCAN_TTIE_TXOE_Msk (0x1U << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
#define FDCAN_TTIE_SE1E_Pos (12U)
#define FDCAN_TTIE_SE1E_Msk (0x1U << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
#define FDCAN_TTIE_SE2E_Pos (13U)
#define FDCAN_TTIE_SE2E_Msk (0x1U << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
#define FDCAN_TTIE_ELCE_Pos (14U)
#define FDCAN_TTIE_ELCE_Msk (0x1U << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
#define FDCAN_TTIE_IWTE_Pos (15U)
#define FDCAN_TTIE_IWTE_Msk (0x1U << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_WTE_Pos (16U)
#define FDCAN_TTIE_WTE_Msk (0x1U << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_AWE_Pos (17U)
#define FDCAN_TTIE_AWE_Msk (0x1U << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
#define FDCAN_TTIE_CERE_Pos (18U)
#define FDCAN_TTIE_CERE_Msk (0x1U << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
/***************** Bit definition for FDCAN_TTILS register ********************/
#define FDCAN_TTILS_SBCS_Pos (0U)
#define FDCAN_TTILS_SBCS_Msk (0x1U << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
#define FDCAN_TTILS_SMCS_Pos (1U)
#define FDCAN_TTILS_SMCS_Msk (0x1U << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
#define FDCAN_TTILS_CSMS_Pos (2U)
#define FDCAN_TTILS_CSMS_Msk (0x1U << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
#define FDCAN_TTILS_SOGS_Pos (3U)
#define FDCAN_TTILS_SOGS_Msk (0x1U << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
#define FDCAN_TTILS_RTMIS_Pos (4U)
#define FDCAN_TTILS_RTMIS_Msk (0x1U << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
#define FDCAN_TTILS_TTMIS_Pos (5U)
#define FDCAN_TTILS_TTMIS_Msk (0x1U << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
#define FDCAN_TTILS_SWES_Pos (6U)
#define FDCAN_TTILS_SWES_Msk (0x1U << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
#define FDCAN_TTILS_GTWS_Pos (7U)
#define FDCAN_TTILS_GTWS_Msk (0x1U << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
#define FDCAN_TTILS_GTDS_Pos (8U)
#define FDCAN_TTILS_GTDS_Msk (0x1U << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
#define FDCAN_TTILS_GTES_Pos (9U)
#define FDCAN_TTILS_GTES_Msk (0x1U << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
#define FDCAN_TTILS_TXUS_Pos (10U)
#define FDCAN_TTILS_TXUS_Msk (0x1U << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
#define FDCAN_TTILS_TXOS_Pos (11U)
#define FDCAN_TTILS_TXOS_Msk (0x1U << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
#define FDCAN_TTILS_SE1S_Pos (12U)
#define FDCAN_TTILS_SE1S_Msk (0x1U << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
#define FDCAN_TTILS_SE2S_Pos (13U)
#define FDCAN_TTILS_SE2S_Msk (0x1U << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
#define FDCAN_TTILS_ELCS_Pos (14U)
#define FDCAN_TTILS_ELCS_Msk (0x1U << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
#define FDCAN_TTILS_IWTS_Pos (15U)
#define FDCAN_TTILS_IWTS_Msk (0x1U << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
#define FDCAN_TTILS_WTS_Pos (16U)
#define FDCAN_TTILS_WTS_Msk (0x1U << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
#define FDCAN_TTILS_AWS_Pos (17U)
#define FDCAN_TTILS_AWS_Msk (0x1U << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
#define FDCAN_TTILS_CERS_Pos (18U)
#define FDCAN_TTILS_CERS_Msk (0x1U << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
/***************** Bit definition for FDCAN_TTOST register ********************/
#define FDCAN_TTOST_EL_Pos (0U)
#define FDCAN_TTOST_EL_Msk (0x3U << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
#define FDCAN_TTOST_MS_Pos (2U)
#define FDCAN_TTOST_MS_Msk (0x3U << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
#define FDCAN_TTOST_SYS_Pos (4U)
#define FDCAN_TTOST_SYS_Msk (0x3U << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
#define FDCAN_TTOST_QGTP_Pos (6U)
#define FDCAN_TTOST_QGTP_Msk (0x1U << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
#define FDCAN_TTOST_QCS_Pos (7U)
#define FDCAN_TTOST_QCS_Msk (0x1U << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
#define FDCAN_TTOST_RTO_Pos (8U)
#define FDCAN_TTOST_RTO_Msk (0xFFU << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
#define FDCAN_TTOST_WGTD_Pos (22U)
#define FDCAN_TTOST_WGTD_Msk (0x1U << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
#define FDCAN_TTOST_GFI_Pos (23U)
#define FDCAN_TTOST_GFI_Msk (0x1U << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
#define FDCAN_TTOST_TMP_Pos (24U)
#define FDCAN_TTOST_TMP_Msk (0x7U << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
#define FDCAN_TTOST_GSI_Pos (27U)
#define FDCAN_TTOST_GSI_Msk (0x1U << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
#define FDCAN_TTOST_WFE_Pos (28U)
#define FDCAN_TTOST_WFE_Msk (0x1U << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
#define FDCAN_TTOST_AWE_Pos (29U)
#define FDCAN_TTOST_AWE_Msk (0x1U << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
#define FDCAN_TTOST_WECS_Pos (30U)
#define FDCAN_TTOST_WECS_Msk (0x1U << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
#define FDCAN_TTOST_SPL_Pos (31U)
#define FDCAN_TTOST_SPL_Msk (0x1U << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
/***************** Bit definition for FDCAN_TURNA register ********************/
#define FDCAN_TURNA_NAV_Pos (0U)
#define FDCAN_TURNA_NAV_Msk (0x3FFFFU << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
/***************** Bit definition for FDCAN_TTLGT register ********************/
#define FDCAN_TTLGT_LT_Pos (0U)
#define FDCAN_TTLGT_LT_Msk (0xFFFFU << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
#define FDCAN_TTLGT_GT_Pos (16U)
#define FDCAN_TTLGT_GT_Msk (0xFFFFU << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
/***************** Bit definition for FDCAN_TTCTC register ********************/
#define FDCAN_TTCTC_CT_Pos (0U)
#define FDCAN_TTCTC_CT_Msk (0xFFFFU << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
#define FDCAN_TTCTC_CC_Pos (16U)
#define FDCAN_TTCTC_CC_Msk (0x3FU << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
/***************** Bit definition for FDCAN_TTCPT register ********************/
#define FDCAN_TTCPT_CCV_Pos (0U)
#define FDCAN_TTCPT_CCV_Msk (0x3FU << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
#define FDCAN_TTCPT_SWV_Pos (16U)
#define FDCAN_TTCPT_SWV_Msk (0xFFFFU << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
/***************** Bit definition for FDCAN_TTCSM register ********************/
#define FDCAN_TTCSM_CSM_Pos (0U)
#define FDCAN_TTCSM_CSM_Msk (0xFFFFU << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
/***************** Bit definition for FDCAN_TTTS register *********************/
#define FDCAN_TTTS_SWTSEL_Pos (0U)
#define FDCAN_TTTS_SWTSEL_Msk (0x3U << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
#define FDCAN_TTTS_EVTSEL_Pos (4U)
#define FDCAN_TTTS_EVTSEL_Msk (0x3U << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
/********************************************************************************/
/* */
/* FDCANCCU (Clock Calibration unit) */
/* */
/********************************************************************************/
/***************** Bit definition for FDCANCCU_CREL register ******************/
#define FDCANCCU_CREL_DAY_Pos (0U)
#define FDCANCCU_CREL_DAY_Msk (0xFFU << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCANCCU_CREL_MON_Pos (8U)
#define FDCANCCU_CREL_MON_Msk (0xFFU << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
#define FDCANCCU_CREL_YEAR_Pos (16U)
#define FDCANCCU_CREL_YEAR_Msk (0xFU << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
#define FDCANCCU_CREL_SUBSTEP_Msk (0xFU << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCANCCU_CREL_STEP_Pos (24U)
#define FDCANCCU_CREL_STEP_Msk (0xFU << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
#define FDCANCCU_CREL_REL_Pos (28U)
#define FDCANCCU_CREL_REL_Msk (0xFU << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCANCCU_CCFG register ******************/
#define FDCANCCU_CCFG_TQBT_Pos (0U)
#define FDCANCCU_CCFG_TQBT_Msk (0x1FU << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
#define FDCANCCU_CCFG_BCC_Pos (6U)
#define FDCANCCU_CCFG_BCC_Msk (0x1U << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
#define FDCANCCU_CCFG_CFL_Pos (7U)
#define FDCANCCU_CCFG_CFL_Msk (0x1U << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
#define FDCANCCU_CCFG_OCPM_Pos (8U)
#define FDCANCCU_CCFG_OCPM_Msk (0xFFU << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
#define FDCANCCU_CCFG_CDIV_Pos (16U)
#define FDCANCCU_CCFG_CDIV_Msk (0xFU << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
#define FDCANCCU_CCFG_SWR_Pos (31U)
#define FDCANCCU_CCFG_SWR_Msk (0x1U << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
/***************** Bit definition for FDCANCCU_CSTAT register *****************/
#define FDCANCCU_CSTAT_OCPC_Pos (0U)
#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFU << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
#define FDCANCCU_CSTAT_TQC_Pos (18U)
#define FDCANCCU_CSTAT_TQC_Msk (0x7FFU << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
#define FDCANCCU_CSTAT_CALS_Pos (30U)
#define FDCANCCU_CSTAT_CALS_Msk (0x3U << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
/****************** Bit definition for FDCANCCU_CWD register ******************/
#define FDCANCCU_CWD_WDC_Pos (0U)
#define FDCANCCU_CWD_WDC_Msk (0xFFFFU << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
#define FDCANCCU_CWD_WDV_Pos (16U)
#define FDCANCCU_CWD_WDV_Msk (0xFFFFU << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
/****************** Bit definition for FDCANCCU_IR register *******************/
#define FDCANCCU_IR_CWE_Pos (0U)
#define FDCANCCU_IR_CWE_Msk (0x1U << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
#define FDCANCCU_IR_CSC_Pos (1U)
#define FDCANCCU_IR_CSC_Msk (0x1U << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
/****************** Bit definition for FDCANCCU_IE register *******************/
#define FDCANCCU_IE_CWEE_Pos (0U)
#define FDCANCCU_IE_CWEE_Msk (0x1U << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
#define FDCANCCU_IE_CSCE_Pos (1U)
#define FDCANCCU_IE_CSCE_Msk (0x1U << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
/******************************************************************************/
/* */
/* HDMI-CEC (CEC) */
/* */
/******************************************************************************/
/******************* Bit definition for CEC_CR register *********************/
#define CEC_CR_CECEN_Pos (0U)
#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
#define CEC_CR_TXSOM_Pos (1U)
#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
#define CEC_CR_TXEOM_Pos (2U)
#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
/******************* Bit definition for CEC_CFGR register *******************/
#define CEC_CFGR_SFT_Pos (0U)
#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
#define CEC_CFGR_RXTOL_Pos (3U)
#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
#define CEC_CFGR_BRESTP_Pos (4U)
#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
#define CEC_CFGR_BREGEN_Pos (5U)
#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
#define CEC_CFGR_LBPEGEN_Pos (6U)
#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
#define CEC_CFGR_SFTOPT_Pos (8U)
#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
#define CEC_CFGR_BRDNOGEN_Pos (7U)
#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
#define CEC_CFGR_OAR_Pos (16U)
#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
#define CEC_CFGR_LSTN_Pos (31U)
#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
/******************* Bit definition for CEC_TXDR register *******************/
#define CEC_TXDR_TXD_Pos (0U)
#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
/******************* Bit definition for CEC_RXDR register *******************/
#define CEC_TXDR_RXD_Pos (0U)
#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
/******************* Bit definition for CEC_ISR register ********************/
#define CEC_ISR_RXBR_Pos (0U)
#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
#define CEC_ISR_RXEND_Pos (1U)
#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
#define CEC_ISR_RXOVR_Pos (2U)
#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
#define CEC_ISR_BRE_Pos (3U)
#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
#define CEC_ISR_SBPE_Pos (4U)
#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
#define CEC_ISR_LBPE_Pos (5U)
#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
#define CEC_ISR_RXACKE_Pos (6U)
#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
#define CEC_ISR_ARBLST_Pos (7U)
#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
#define CEC_ISR_TXBR_Pos (8U)
#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
#define CEC_ISR_TXEND_Pos (9U)
#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
#define CEC_ISR_TXUDR_Pos (10U)
#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
#define CEC_ISR_TXERR_Pos (11U)
#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
#define CEC_ISR_TXACKE_Pos (12U)
#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
/******************* Bit definition for CEC_IER register ********************/
#define CEC_IER_RXBRIE_Pos (0U)
#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
#define CEC_IER_RXENDIE_Pos (1U)
#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
#define CEC_IER_RXOVRIE_Pos (2U)
#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
#define CEC_IER_BREIE_Pos (3U)
#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
#define CEC_IER_SBPEIE_Pos (4U)
#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
#define CEC_IER_LBPEIE_Pos (5U)
#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
#define CEC_IER_RXACKEIE_Pos (6U)
#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
#define CEC_IER_ARBLSTIE_Pos (7U)
#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
#define CEC_IER_TXBRIE_Pos (8U)
#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
#define CEC_IER_TXENDIE_Pos (9U)
#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
#define CEC_IER_TXUDRIE_Pos (10U)
#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
#define CEC_IER_TXERRIE_Pos (11U)
#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE_Pos (12U)
#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Crypto Processor */
/* */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register ********************/
#define CRYP_CR_ALGODIR_Pos (2U)
#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
#define CRYP_CR_ALGOMODE_Pos (3U)
#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1U << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001U << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
#define CRYP_CR_DATATYPE_Pos (6U)
#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
#define CRYP_CR_KEYSIZE_Pos (8U)
#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
#define CRYP_CR_FFLUSH_Pos (14U)
#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
#define CRYP_CR_CRYPEN_Pos (15U)
#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
#define CRYP_CR_GCM_CCMPH_Pos (16U)
#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
/****************** Bits definition for CRYP_SR register *********************/
#define CRYP_SR_IFEM_Pos (0U)
#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
#define CRYP_SR_IFNF_Pos (1U)
#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
#define CRYP_SR_OFNE_Pos (2U)
#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
#define CRYP_SR_OFFU_Pos (3U)
#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
#define CRYP_SR_BUSY_Pos (4U)
#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
/****************** Bits definition for CRYP_DMACR register ******************/
#define CRYP_DMACR_DIEN_Pos (0U)
#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
#define CRYP_DMACR_DOEN_Pos (1U)
#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
/***************** Bits definition for CRYP_IMSCR register ******************/
#define CRYP_IMSCR_INIM_Pos (0U)
#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
#define CRYP_IMSCR_OUTIM_Pos (1U)
#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
/****************** Bits definition for CRYP_RISR register *******************/
#define CRYP_RISR_INRIS_Pos (0U)
#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */
#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
#define CRYP_RISR_OUTRIS_Pos (1U)
#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */
#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
/****************** Bits definition for CRYP_MISR register *******************/
#define CRYP_MISR_INMIS_Pos (0U)
#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
#define CRYP_MISR_OUTMIS_Pos (1U)
#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR1_TSAMPLE2_Pos (0U)
#define DAC_SHSR1_TSAMPLE2_Msk (0x3FFU << DAC_SHSR1_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE2 DAC_SHSR1_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE_Pos (0U)
#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
#define DCMI_CR_CM_Pos (1U)
#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
#define DCMI_CR_CM DCMI_CR_CM_Msk
#define DCMI_CR_CROP_Pos (2U)
#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
#define DCMI_CR_CROP DCMI_CR_CROP_Msk
#define DCMI_CR_JPEG_Pos (3U)
#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
#define DCMI_CR_ESS_Pos (4U)
#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
#define DCMI_CR_ESS DCMI_CR_ESS_Msk
#define DCMI_CR_PCKPOL_Pos (5U)
#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
#define DCMI_CR_HSPOL_Pos (6U)
#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
#define DCMI_CR_VSPOL_Pos (7U)
#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
#define DCMI_CR_CRE_Pos (12U)
#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
#define DCMI_CR_ENABLE_Pos (14U)
#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
#define DCMI_CR_BSM_Pos (16U)
#define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
#define DCMI_CR_BSM DCMI_CR_BSM_Msk
#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
#define DCMI_CR_OEBS_Pos (18U)
#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
#define DCMI_CR_LSM_Pos (19U)
#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
#define DCMI_CR_LSM DCMI_CR_LSM_Msk
#define DCMI_CR_OELS_Pos (20U)
#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
#define DCMI_CR_OELS DCMI_CR_OELS_Msk
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC_Pos (0U)
#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
#define DCMI_SR_VSYNC_Pos (1U)
#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
#define DCMI_SR_FNE_Pos (2U)
#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
#define DCMI_SR_FNE DCMI_SR_FNE_Msk
/******************** Bits definition for DCMI_RIS register ****************/
#define DCMI_RIS_FRAME_RIS_Pos (0U)
#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
#define DCMI_RIS_OVR_RIS_Pos (1U)
#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
#define DCMI_RIS_ERR_RIS_Pos (2U)
#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
#define DCMI_RIS_VSYNC_RIS_Pos (3U)
#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
#define DCMI_RIS_LINE_RIS_Pos (4U)
#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE_Pos (0U)
#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
#define DCMI_IER_OVR_IE_Pos (1U)
#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
#define DCMI_IER_ERR_IE_Pos (2U)
#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
#define DCMI_IER_VSYNC_IE_Pos (3U)
#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
#define DCMI_IER_LINE_IE_Pos (4U)
#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
/******************** Bits definition for DCMI_MIS register *****************/
#define DCMI_MIS_FRAME_MIS_Pos (0U)
#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
#define DCMI_MIS_OVR_MIS_Pos (1U)
#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
#define DCMI_MIS_ERR_MIS_Pos (2U)
#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
#define DCMI_MIS_VSYNC_MIS_Pos (3U)
#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
#define DCMI_MIS_LINE_MIS_Pos (4U)
#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC_Pos (0U)
#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
#define DCMI_ICR_OVR_ISC_Pos (1U)
#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
#define DCMI_ICR_ERR_ISC_Pos (2U)
#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
#define DCMI_ICR_VSYNC_ISC_Pos (3U)
#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
#define DCMI_ICR_LINE_ISC_Pos (4U)
#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
/******************** Bits definition for DCMI_ESCR register ******************/
#define DCMI_ESCR_FSC_Pos (0U)
#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
#define DCMI_ESCR_LSC_Pos (8U)
#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
#define DCMI_ESCR_LEC_Pos (16U)
#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
#define DCMI_ESCR_FEC_Pos (24U)
#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
/******************** Bits definition for DCMI_ESUR register ******************/
#define DCMI_ESUR_FSU_Pos (0U)
#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
#define DCMI_ESUR_LSU_Pos (8U)
#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
#define DCMI_ESUR_LEU_Pos (16U)
#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
#define DCMI_ESUR_FEU_Pos (24U)
#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
/******************** Bits definition for DCMI_CWSTRT register ******************/
#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
#define DCMI_CWSTRT_VST_Pos (16U)
#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
/******************** Bits definition for DCMI_CWSIZE register ******************/
#define DCMI_CWSIZE_CAPCNT_Pos (0U)
#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
#define DCMI_CWSIZE_VLINE_Pos (16U)
#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
/******************** Bits definition for DCMI_DR register ******************/
#define DCMI_DR_BYTE0_Pos (0U)
#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
#define DCMI_DR_BYTE1_Pos (8U)
#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
#define DCMI_DR_BYTE2_Pos (16U)
#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
#define DCMI_DR_BYTE3_Pos (24U)
#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
/******************************************************************************/
/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
/**************** DFSDM channel configuration registers ********************/
/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
#define DFSDM_CHCFGR1_CHEN_Pos (7U)
#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
#define DFSDM_CHCFGR1_SITP_Pos (0U)
#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
/**************** Bit definition for DFSDM_CHWDATR register *******************/
#define DFSDM_CHWDATR_WDATA_Pos (0U)
#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
/**************** Bit definition for DFSDM_CHDATINR register *****************/
#define DFSDM_CHDATINR_INDAT0_Pos (0U)
#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
#define DFSDM_CHDATINR_INDAT1_Pos (16U)
#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
/************************ DFSDM module registers ****************************/
/******************** Bit definition for DFSDM_FLTCR1 register *******************/
#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
#define DFSDM_FLTCR1_FAST_Pos (29U)
#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
#define DFSDM_FLTCR1_RCH_Pos (24U)
#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
#define DFSDM_FLTCR1_RSYNC_Pos (19U)
#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
#define DFSDM_FLTCR1_RCONT_Pos (18U)
#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
#define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
#define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
#define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
#define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
#define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
#define DFSDM_FLTCR1_JSCAN_Pos (4U)
#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
#define DFSDM_FLTCR1_JSYNC_Pos (3U)
#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
#define DFSDM_FLTCR1_DFEN_Pos (0U)
#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
/******************** Bit definition for DFSDM_FLTCR2 register *******************/
#define DFSDM_FLTCR2_AWDCH_Pos (16U)
#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
#define DFSDM_FLTCR2_EXCH_Pos (8U)
#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
#define DFSDM_FLTCR2_CKABIE_Pos (6U)
#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
#define DFSDM_FLTCR2_SCDIE_Pos (5U)
#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
#define DFSDM_FLTCR2_AWDIE_Pos (4U)
#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
#define DFSDM_FLTCR2_REOCIE_Pos (1U)
#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
/******************** Bit definition for DFSDM_FLTISR register *******************/
#define DFSDM_FLTISR_SCDF_Pos (24U)
#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
#define DFSDM_FLTISR_CKABF_Pos (16U)
#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
#define DFSDM_FLTISR_RCIP_Pos (14U)
#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
#define DFSDM_FLTISR_JCIP_Pos (13U)
#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
#define DFSDM_FLTISR_AWDF_Pos (4U)
#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
#define DFSDM_FLTISR_ROVRF_Pos (3U)
#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
#define DFSDM_FLTISR_JOVRF_Pos (2U)
#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
#define DFSDM_FLTISR_REOCF_Pos (1U)
#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
#define DFSDM_FLTISR_JEOCF_Pos (0U)
#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
/******************** Bit definition for DFSDM_FLTICR register *******************/
#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
/******************** Bit definition for DFSDM_FLTFCR register *******************/
#define DFSDM_FLTFCR_FORD_Pos (29U)
#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
#define DFSDM_FLTFCR_FOSR_Pos (16U)
#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
#define DFSDM_FLTFCR_IOSR_Pos (0U)
#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
/****************** Bit definition for DFSDM_FLTAWSR register ******************/
#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
/******************************************************************************/
/* */
/* BDMA Controller */
/* */
/******************************************************************************/
/******************* Bit definition for BDMA_ISR register ********************/
#define BDMA_ISR_GIF0_Pos (0U)
#define BDMA_ISR_GIF0_Msk (0x1U << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
#define BDMA_ISR_TCIF0_Pos (1U)
#define BDMA_ISR_TCIF0_Msk (0x1U << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
#define BDMA_ISR_HTIF0_Pos (2U)
#define BDMA_ISR_HTIF0_Msk (0x1U << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
#define BDMA_ISR_TEIF0_Pos (3U)
#define BDMA_ISR_TEIF0_Msk (0x1U << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
#define BDMA_ISR_GIF1_Pos (4U)
#define BDMA_ISR_GIF1_Msk (0x1U << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define BDMA_ISR_TCIF1_Pos (5U)
#define BDMA_ISR_TCIF1_Msk (0x1U << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define BDMA_ISR_HTIF1_Pos (6U)
#define BDMA_ISR_HTIF1_Msk (0x1U << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define BDMA_ISR_TEIF1_Pos (7U)
#define BDMA_ISR_TEIF1_Msk (0x1U << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define BDMA_ISR_GIF2_Pos (8U)
#define BDMA_ISR_GIF2_Msk (0x1U << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define BDMA_ISR_TCIF2_Pos (9U)
#define BDMA_ISR_TCIF2_Msk (0x1U << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define BDMA_ISR_HTIF2_Pos (10U)
#define BDMA_ISR_HTIF2_Msk (0x1U << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define BDMA_ISR_TEIF2_Pos (11U)
#define BDMA_ISR_TEIF2_Msk (0x1U << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define BDMA_ISR_GIF3_Pos (12U)
#define BDMA_ISR_GIF3_Msk (0x1U << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define BDMA_ISR_TCIF3_Pos (13U)
#define BDMA_ISR_TCIF3_Msk (0x1U << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define BDMA_ISR_HTIF3_Pos (14U)
#define BDMA_ISR_HTIF3_Msk (0x1U << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define BDMA_ISR_TEIF3_Pos (15U)
#define BDMA_ISR_TEIF3_Msk (0x1U << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define BDMA_ISR_GIF4_Pos (16U)
#define BDMA_ISR_GIF4_Msk (0x1U << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define BDMA_ISR_TCIF4_Pos (17U)
#define BDMA_ISR_TCIF4_Msk (0x1U << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define BDMA_ISR_HTIF4_Pos (18U)
#define BDMA_ISR_HTIF4_Msk (0x1U << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define BDMA_ISR_TEIF4_Pos (19U)
#define BDMA_ISR_TEIF4_Msk (0x1U << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define BDMA_ISR_GIF5_Pos (20U)
#define BDMA_ISR_GIF5_Msk (0x1U << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define BDMA_ISR_TCIF5_Pos (21U)
#define BDMA_ISR_TCIF5_Msk (0x1U << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define BDMA_ISR_HTIF5_Pos (22U)
#define BDMA_ISR_HTIF5_Msk (0x1U << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define BDMA_ISR_TEIF5_Pos (23U)
#define BDMA_ISR_TEIF5_Msk (0x1U << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define BDMA_ISR_GIF6_Pos (24U)
#define BDMA_ISR_GIF6_Msk (0x1U << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define BDMA_ISR_TCIF6_Pos (25U)
#define BDMA_ISR_TCIF6_Msk (0x1U << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define BDMA_ISR_HTIF6_Pos (26U)
#define BDMA_ISR_HTIF6_Msk (0x1U << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define BDMA_ISR_TEIF6_Pos (27U)
#define BDMA_ISR_TEIF6_Msk (0x1U << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define BDMA_ISR_GIF7_Pos (28U)
#define BDMA_ISR_GIF7_Msk (0x1U << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define BDMA_ISR_TCIF7_Pos (29U)
#define BDMA_ISR_TCIF7_Msk (0x1U << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define BDMA_ISR_HTIF7_Pos (30U)
#define BDMA_ISR_HTIF7_Msk (0x1U << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define BDMA_ISR_TEIF7_Pos (31U)
#define BDMA_ISR_TEIF7_Msk (0x1U << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for BDMA_IFCR register *******************/
#define BDMA_IFCR_CGIF0_Pos (0U)
#define BDMA_IFCR_CGIF0_Msk (0x1U << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
#define BDMA_IFCR_CTCIF0_Pos (1U)
#define BDMA_IFCR_CTCIF0_Msk (0x1U << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
#define BDMA_IFCR_CHTIF0_Pos (2U)
#define BDMA_IFCR_CHTIF0_Msk (0x1U << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
#define BDMA_IFCR_CTEIF0_Pos (3U)
#define BDMA_IFCR_CTEIF0_Msk (0x1U << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
#define BDMA_IFCR_CGIF1_Pos (4U)
#define BDMA_IFCR_CGIF1_Msk (0x1U << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
#define BDMA_IFCR_CTCIF1_Pos (5U)
#define BDMA_IFCR_CTCIF1_Msk (0x1U << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define BDMA_IFCR_CHTIF1_Pos (6U)
#define BDMA_IFCR_CHTIF1_Msk (0x1U << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define BDMA_IFCR_CTEIF1_Pos (7U)
#define BDMA_IFCR_CTEIF1_Msk (0x1U << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define BDMA_IFCR_CGIF2_Pos (8U)
#define BDMA_IFCR_CGIF2_Msk (0x1U << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define BDMA_IFCR_CTCIF2_Pos (9U)
#define BDMA_IFCR_CTCIF2_Msk (0x1U << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define BDMA_IFCR_CHTIF2_Pos (10U)
#define BDMA_IFCR_CHTIF2_Msk (0x1U << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define BDMA_IFCR_CTEIF2_Pos (11U)
#define BDMA_IFCR_CTEIF2_Msk (0x1U << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define BDMA_IFCR_CGIF3_Pos (12U)
#define BDMA_IFCR_CGIF3_Msk (0x1U << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define BDMA_IFCR_CTCIF3_Pos (13U)
#define BDMA_IFCR_CTCIF3_Msk (0x1U << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define BDMA_IFCR_CHTIF3_Pos (14U)
#define BDMA_IFCR_CHTIF3_Msk (0x1U << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define BDMA_IFCR_CTEIF3_Pos (15U)
#define BDMA_IFCR_CTEIF3_Msk (0x1U << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define BDMA_IFCR_CGIF4_Pos (16U)
#define BDMA_IFCR_CGIF4_Msk (0x1U << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define BDMA_IFCR_CTCIF4_Pos (17U)
#define BDMA_IFCR_CTCIF4_Msk (0x1U << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define BDMA_IFCR_CHTIF4_Pos (18U)
#define BDMA_IFCR_CHTIF4_Msk (0x1U << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define BDMA_IFCR_CTEIF4_Pos (19U)
#define BDMA_IFCR_CTEIF4_Msk (0x1U << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define BDMA_IFCR_CGIF5_Pos (20U)
#define BDMA_IFCR_CGIF5_Msk (0x1U << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define BDMA_IFCR_CTCIF5_Pos (21U)
#define BDMA_IFCR_CTCIF5_Msk (0x1U << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define BDMA_IFCR_CHTIF5_Pos (22U)
#define BDMA_IFCR_CHTIF5_Msk (0x1U << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define BDMA_IFCR_CTEIF5_Pos (23U)
#define BDMA_IFCR_CTEIF5_Msk (0x1U << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define BDMA_IFCR_CGIF6_Pos (24U)
#define BDMA_IFCR_CGIF6_Msk (0x1U << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define BDMA_IFCR_CTCIF6_Pos (25U)
#define BDMA_IFCR_CTCIF6_Msk (0x1U << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define BDMA_IFCR_CHTIF6_Pos (26U)
#define BDMA_IFCR_CHTIF6_Msk (0x1U << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define BDMA_IFCR_CTEIF6_Pos (27U)
#define BDMA_IFCR_CTEIF6_Msk (0x1U << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define BDMA_IFCR_CGIF7_Pos (28U)
#define BDMA_IFCR_CGIF7_Msk (0x1U << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define BDMA_IFCR_CTCIF7_Pos (29U)
#define BDMA_IFCR_CTCIF7_Msk (0x1U << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define BDMA_IFCR_CHTIF7_Pos (30U)
#define BDMA_IFCR_CHTIF7_Msk (0x1U << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define BDMA_IFCR_CTEIF7_Pos (31U)
#define BDMA_IFCR_CTEIF7_Msk (0x1U << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for BDMA_CCR register ********************/
#define BDMA_CCR_EN_Pos (0U)
#define BDMA_CCR_EN_Msk (0x1U << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
#define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
#define BDMA_CCR_TCIE_Pos (1U)
#define BDMA_CCR_TCIE_Msk (0x1U << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define BDMA_CCR_HTIE_Pos (2U)
#define BDMA_CCR_HTIE_Msk (0x1U << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define BDMA_CCR_TEIE_Pos (3U)
#define BDMA_CCR_TEIE_Msk (0x1U << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define BDMA_CCR_DIR_Pos (4U)
#define BDMA_CCR_DIR_Msk (0x1U << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
#define BDMA_CCR_CIRC_Pos (5U)
#define BDMA_CCR_CIRC_Msk (0x1U << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
#define BDMA_CCR_PINC_Pos (6U)
#define BDMA_CCR_PINC_Msk (0x1U << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define BDMA_CCR_MINC_Pos (7U)
#define BDMA_CCR_MINC_Msk (0x1U << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
#define BDMA_CCR_PSIZE_Pos (8U)
#define BDMA_CCR_PSIZE_Msk (0x3U << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define BDMA_CCR_PSIZE_0 (0x1U << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define BDMA_CCR_PSIZE_1 (0x2U << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define BDMA_CCR_MSIZE_Pos (10U)
#define BDMA_CCR_MSIZE_Msk (0x3U << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define BDMA_CCR_MSIZE_0 (0x1U << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define BDMA_CCR_MSIZE_1 (0x2U << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define BDMA_CCR_PL_Pos (12U)
#define BDMA_CCR_PL_Msk (0x3U << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
#define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define BDMA_CCR_PL_0 (0x1U << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
#define BDMA_CCR_PL_1 (0x2U << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
#define BDMA_CCR_MEM2MEM_Pos (14U)
#define BDMA_CCR_MEM2MEM_Msk (0x1U << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for BDMA_CNDTR register *******************/
#define BDMA_CNDTR_NDT_Pos (0U)
#define BDMA_CNDTR_NDT_Msk (0xFFFFU << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for BDMA_CPAR register ********************/
#define BDMA_CPAR_PA_Pos (0U)
#define BDMA_CPAR_PA_Msk (0xFFFFFFFFU << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for BDMA_CMAR register ********************/
#define BDMA_CMAR_MA_Pos (0U)
#define BDMA_CMAR_MA_Msk (0xFFFFFFFFU << BDMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define BDMA_CMAR_MA BDMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* Ethernet MAC Registers bits definitions */
/* */
/******************************************************************************/
/* Bit definition for Ethernet MAC Configuration Register register */
#define ETH_MACCR_ARP_Pos (31U)
#define ETH_MACCR_ARP_Msk (0x1U << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
#define ETH_MACCR_SARC_Pos (28U)
#define ETH_MACCR_SARC_Msk (0x7U << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1U << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
#define ETH_MACCR_SARC_INSADDR1_Msk (0x3U << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
#define ETH_MACCR_SARC_REPADDR0_Msk (0x3U << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
#define ETH_MACCR_SARC_REPADDR1_Msk (0x7U << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_IPC_Pos (27U)
#define ETH_MACCR_IPC_Msk (0x1U << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
#define ETH_MACCR_IPG_Pos (24U)
#define ETH_MACCR_IPG_Msk (0x7U << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
#define ETH_MACCR_GPSLCE_Pos (23U)
#define ETH_MACCR_GPSLCE_Msk (0x1U << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
#define ETH_MACCR_S2KP_Pos (22U)
#define ETH_MACCR_S2KP_Msk (0x1U << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
#define ETH_MACCR_CST_Pos (21U)
#define ETH_MACCR_CST_Msk (0x1U << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
#define ETH_MACCR_ACS_Pos (20U)
#define ETH_MACCR_ACS_Msk (0x1U << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
#define ETH_MACCR_WD_Pos (19U)
#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
#define ETH_MACCR_JD_Pos (17U)
#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
#define ETH_MACCR_JE_Pos (16U)
#define ETH_MACCR_JE_Msk (0x1U << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
#define ETH_MACCR_FES_Pos (14U)
#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
#define ETH_MACCR_DM_Pos (13U)
#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
#define ETH_MACCR_LM_Pos (12U)
#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
#define ETH_MACCR_ECRSFD_Pos (11U)
#define ETH_MACCR_ECRSFD_Msk (0x1U << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
#define ETH_MACCR_DO_Pos (10U)
#define ETH_MACCR_DO_Msk (0x1U << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
#define ETH_MACCR_DCRS_Pos (9U)
#define ETH_MACCR_DCRS_Msk (0x1U << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
#define ETH_MACCR_DR_Pos (8U)
#define ETH_MACCR_DR_Msk (0x1U << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
#define ETH_MACCR_BL_Pos (5U)
#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
#define ETH_MACCR_BL_10 (0x0U << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
#define ETH_MACCR_BL_8 (0x1U << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
#define ETH_MACCR_BL_4 (0x2U << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
#define ETH_MACCR_BL_1 (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_DC_Pos (4U)
#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
#define ETH_MACCR_PRELEN_Pos (2U)
#define ETH_MACCR_PRELEN_Msk (0x3U << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
#define ETH_MACCR_PRELEN_7 (0x0U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
#define ETH_MACCR_PRELEN_5 (0x1U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
#define ETH_MACCR_PRELEN_3 (0x2U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
#define ETH_MACCR_TE_Pos (1U)
#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
#define ETH_MACCR_RE_Pos (0U)
#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
/* Bit definition for Ethernet MAC Extended Configuration Register register */
#define ETH_MACECR_EIPG_Pos (25U)
#define ETH_MACECR_EIPG_Msk (0x1FU << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
#define ETH_MACECR_EIPGEN_Pos (24U)
#define ETH_MACECR_EIPGEN_Msk (0x1U << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
#define ETH_MACECR_USP_Pos (18U)
#define ETH_MACECR_USP_Msk (0x1U << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
#define ETH_MACECR_SPEN_Pos (17U)
#define ETH_MACECR_SPEN_Msk (0x1U << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
#define ETH_MACECR_DCRCC_Pos (16U)
#define ETH_MACECR_DCRCC_Msk (0x1U << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
#define ETH_MACECR_GPSL_Pos (0U)
#define ETH_MACECR_GPSL_Msk (0x3FFFU << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
/* Bit definition for Ethernet MAC Packet Filter Register */
#define ETH_MACPFR_RA_Pos (31U)
#define ETH_MACPFR_RA_Msk (0x1U << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
#define ETH_MACPFR_DNTU_Pos (21U)
#define ETH_MACPFR_DNTU_Msk (0x1U << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
#define ETH_MACPFR_IPFE_Pos (20U)
#define ETH_MACPFR_IPFE_Msk (0x1U << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
#define ETH_MACPFR_VTFE_Pos (16U)
#define ETH_MACPFR_VTFE_Msk (0x1U << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
#define ETH_MACPFR_HPF_Pos (10U)
#define ETH_MACPFR_HPF_Msk (0x1U << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
#define ETH_MACPFR_SAF_Pos (9U)
#define ETH_MACPFR_SAF_Msk (0x1U << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
#define ETH_MACPFR_SAIF_Pos (8U)
#define ETH_MACPFR_SAIF_Msk (0x1U << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
#define ETH_MACPFR_PCF_Pos (6U)
#define ETH_MACPFR_PCF_Msk (0x3U << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1U << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1U << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3U << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACPFR_DBF_Pos (5U)
#define ETH_MACPFR_DBF_Msk (0x1U << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
#define ETH_MACPFR_PM_Pos (4U)
#define ETH_MACPFR_PM_Msk (0x1U << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
#define ETH_MACPFR_DAIF_Pos (3U)
#define ETH_MACPFR_DAIF_Msk (0x1U << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
#define ETH_MACPFR_HMC_Pos (2U)
#define ETH_MACPFR_HMC_Msk (0x1U << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
#define ETH_MACPFR_HUC_Pos (1U)
#define ETH_MACPFR_HUC_Msk (0x1U << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
#define ETH_MACPFR_PR_Pos (0U)
#define ETH_MACPFR_PR_Msk (0x1U << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
/* Bit definition for Ethernet MAC Watchdog Timeout Register */
#define ETH_MACWTR_PWE_Pos (8U)
#define ETH_MACWTR_PWE_Msk (0x1U << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
#define ETH_MACWTR_WTO_Pos (0U)
#define ETH_MACWTR_WTO_Msk (0xFU << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH_Pos (0U)
#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL_Pos (0U)
#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVTR_EIVLRXS_Pos (31U)
#define ETH_MACVTR_EIVLRXS_Msk (0x1U << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
#define ETH_MACVTR_EIVLS_Pos (28U)
#define ETH_MACVTR_EIVLS_Msk (0x3U << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1U << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1U << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3U << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTR_ERIVLT_Pos (27U)
#define ETH_MACVTR_ERIVLT_Msk (0x1U << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
#define ETH_MACVTR_EDVLP_Pos (26U)
#define ETH_MACVTR_EDVLP_Msk (0x1U << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
#define ETH_MACVTR_VTHM_Pos (25U)
#define ETH_MACVTR_VTHM_Msk (0x1U << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
#define ETH_MACVTR_EVLRXS_Pos (24U)
#define ETH_MACVTR_EVLRXS_Msk (0x1U << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
#define ETH_MACVTR_EVLS_Pos (21U)
#define ETH_MACVTR_EVLS_Msk (0x3U << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1U << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1U << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3U << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTR_DOVLTC_Pos (20U)
#define ETH_MACVTR_DOVLTC_Msk (0x1U << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
#define ETH_MACVTR_ERSVLM_Pos (19U)
#define ETH_MACVTR_ERSVLM_Msk (0x1U << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
#define ETH_MACVTR_ESVL_Pos (18U)
#define ETH_MACVTR_ESVL_Msk (0x1U << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
#define ETH_MACVTR_VTIM_Pos (17U)
#define ETH_MACVTR_VTIM_Msk (0x1U << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
#define ETH_MACVTR_ETV_Pos (16U)
#define ETH_MACVTR_ETV_Msk (0x1U << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
#define ETH_MACVTR_VL_Pos (0U)
#define ETH_MACVTR_VL_Msk (0xFFFFU << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
#define ETH_MACVTR_VL_UP_Pos (13U)
#define ETH_MACVTR_VL_UP_Msk (0x7U << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
#define ETH_MACVTR_VL_CFIDEI_Msk (0x1U << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACVTR_VL_VID_Pos (0U)
#define ETH_MACVTR_VL_VID_Msk (0xFFFU << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
/* Bit definition for Ethernet MAC VLAN Hash Table Register */
#define ETH_MACVHTR_VLHT_Pos (0U)
#define ETH_MACVHTR_VLHT_Msk (0xFFFFU << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
/* Bit definition for Ethernet MAC VLAN Incl Register */
#define ETH_MACVIR_VLTI_Pos (20U)
#define ETH_MACVIR_VLTI_Msk (0x1U << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
#define ETH_MACVIR_CSVL_Pos (19U)
#define ETH_MACVIR_CSVL_Msk (0x1U << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define ETH_MACVIR_VLP_Pos (18U)
#define ETH_MACVIR_VLP_Msk (0x1U << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
#define ETH_MACVIR_VLC_Pos (16U)
#define ETH_MACVIR_VLC_Msk (0x3U << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1U << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1U << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3U << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACVIR_VLT_Pos (0U)
#define ETH_MACVIR_VLT_Msk (0xFFFFU << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define ETH_MACVIR_VLT_UP_Pos (13U)
#define ETH_MACVIR_VLT_UP_Msk (0x7U << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1U << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACVIR_VLT_VID_Pos (0U)
#define ETH_MACVIR_VLT_VID_Msk (0xFFFU << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
#define ETH_MACIVIR_VLTI_Pos (20U)
#define ETH_MACIVIR_VLTI_Msk (0x1U << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
#define ETH_MACIVIR_CSVL_Pos (19U)
#define ETH_MACIVIR_CSVL_Msk (0x1U << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define ETH_MACIVIR_VLP_Pos (18U)
#define ETH_MACIVIR_VLP_Msk (0x1U << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
#define ETH_MACIVIR_VLC_Pos (16U)
#define ETH_MACIVIR_VLC_Msk (0x3U << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1U << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1U << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3U << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACIVIR_VLT_Pos (0U)
#define ETH_MACIVIR_VLT_Msk (0xFFFFU << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define ETH_MACIVIR_VLT_UP_Pos (13U)
#define ETH_MACIVIR_VLT_UP_Msk (0x7U << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1U << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACIVIR_VLT_VID_Pos (0U)
#define ETH_MACIVIR_VLT_VID_Msk (0xFFFU << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
#define ETH_MACTFCR_PT_Pos (16U)
#define ETH_MACTFCR_PT_Msk (0xFFFFU << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
#define ETH_MACTFCR_DZPQ_Pos (7U)
#define ETH_MACTFCR_DZPQ_Msk (0x1U << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
#define ETH_MACTFCR_PLT_Pos (4U)
#define ETH_MACTFCR_PLT_Msk (0x7U << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1U << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1U << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3U << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1U << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5U << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
#define ETH_MACTFCR_TFE_Pos (1U)
#define ETH_MACTFCR_TFE_Msk (0x1U << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
#define ETH_MACTFCR_FCB_Pos (0U)
#define ETH_MACTFCR_FCB_Msk (0x1U << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
#define ETH_MACRFCR_UP_Pos (1U)
#define ETH_MACRFCR_UP_Msk (0x1U << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
#define ETH_MACRFCR_RFE_Pos (0U)
#define ETH_MACRFCR_RFE_Msk (0x1U << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
/* Bit definition for Ethernet MAC Interrupt Status Register */
#define ETH_MACISR_RXSTSIS_Pos (14U)
#define ETH_MACISR_RXSTSIS_Msk (0x1U << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
#define ETH_MACISR_TXSTSIS_Pos (13U)
#define ETH_MACISR_TXSTSIS_Msk (0x1U << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
#define ETH_MACISR_TSIS_Pos (12U)
#define ETH_MACISR_TSIS_Msk (0x1U << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
#define ETH_MACISR_MMCTXIS_Pos (10U)
#define ETH_MACISR_MMCTXIS_Msk (0x1U << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
#define ETH_MACISR_MMCRXIS_Pos (9U)
#define ETH_MACISR_MMCRXIS_Msk (0x1U << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
#define ETH_MACISR_MMCIS_Pos (8U)
#define ETH_MACISR_MMCIS_Msk (0x1U << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
#define ETH_MACISR_LPIIS_Pos (5U)
#define ETH_MACISR_LPIIS_Msk (0x1U << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
#define ETH_MACISR_PMTIS_Pos (4U)
#define ETH_MACISR_PMTIS_Msk (0x1U << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
#define ETH_MACISR_PHYIS_Pos (3U)
#define ETH_MACISR_PHYIS_Msk (0x1U << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
/* Bit definition for Ethernet MAC Interrupt Enable Register */
#define ETH_MACIER_RXSTSIE_Pos (14U)
#define ETH_MACIER_RXSTSIE_Msk (0x1U << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
#define ETH_MACIER_TXSTSIE_Pos (13U)
#define ETH_MACIER_TXSTSIE_Msk (0x1U << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
#define ETH_MACIER_TSIE_Pos (12U)
#define ETH_MACIER_TSIE_Msk (0x1U << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
#define ETH_MACIER_LPIIE_Pos (5U)
#define ETH_MACIER_LPIIE_Msk (0x1U << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
#define ETH_MACIER_PMTIE_Pos (4U)
#define ETH_MACIER_PMTIE_Msk (0x1U << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
#define ETH_MACIER_PHYIE_Pos (3U)
#define ETH_MACIER_PHYIE_Msk (0x1U << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
/* Bit definition for Ethernet MAC Rx Tx Status Register */
#define ETH_MACRXTXSR_RWT_Pos (8U)
#define ETH_MACRXTXSR_RWT_Msk (0x1U << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
#define ETH_MACRXTXSR_EXCOL_Pos (5U)
#define ETH_MACRXTXSR_EXCOL_Msk (0x1U << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
#define ETH_MACRXTXSR_LCOL_Pos (4U)
#define ETH_MACRXTXSR_LCOL_Msk (0x1U << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
#define ETH_MACRXTXSR_EXDEF_Pos (3U)
#define ETH_MACRXTXSR_EXDEF_Msk (0x1U << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
#define ETH_MACRXTXSR_LCARR_Pos (2U)
#define ETH_MACRXTXSR_LCARR_Msk (0x1U << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
#define ETH_MACRXTXSR_NCARR_Pos (1U)
#define ETH_MACRXTXSR_NCARR_Msk (0x1U << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
#define ETH_MACRXTXSR_TJT_Pos (0U)
#define ETH_MACRXTXSR_TJT_Msk (0x1U << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
/* Bit definition for Ethernet MAC PMT Control Status Register */
#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
#define ETH_MACPCSR_RWKFILTRST_Msk (0x1U << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
#define ETH_MACPCSR_RWKPTR_Pos (24U)
#define ETH_MACPCSR_RWKPTR_Msk (0x1FU << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
#define ETH_MACPCSR_RWKPFE_Pos (10U)
#define ETH_MACPCSR_RWKPFE_Msk (0x1U << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
#define ETH_MACPCSR_GLBLUCAST_Msk (0x1U << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
#define ETH_MACPCSR_RWKPRCVD_Msk (0x1U << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
#define ETH_MACPCSR_MGKPRCVD_Msk (0x1U << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
#define ETH_MACPCSR_RWKPKTEN_Msk (0x1U << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
#define ETH_MACPCSR_MGKPKTEN_Msk (0x1U << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
#define ETH_MACPCSR_PWRDWN_Pos (0U)
#define ETH_MACPCSR_PWRDWN_Msk (0x1U << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
#define ETH_MACRWUPFR_D_Pos (0U)
#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
/* Bit definition for Ethernet MAC LPI Control Status Register */
#define ETH_MACLCSR_LPITCSE_Pos (21U)
#define ETH_MACLCSR_LPITCSE_Msk (0x1U << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
#define ETH_MACLCSR_LPITE_Pos (20U)
#define ETH_MACLCSR_LPITE_Msk (0x1U << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
#define ETH_MACLCSR_LPITXA_Pos (19U)
#define ETH_MACLCSR_LPITXA_Msk (0x1U << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
#define ETH_MACLCSR_PLS_Pos (17U)
#define ETH_MACLCSR_PLS_Msk (0x1U << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
#define ETH_MACLCSR_LPIEN_Pos (16U)
#define ETH_MACLCSR_LPIEN_Msk (0x1U << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
#define ETH_MACLCSR_RLPIST_Pos (9U)
#define ETH_MACLCSR_RLPIST_Msk (0x1U << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
#define ETH_MACLCSR_TLPIST_Pos (8U)
#define ETH_MACLCSR_TLPIST_Msk (0x1U << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
#define ETH_MACLCSR_RLPIEX_Pos (3U)
#define ETH_MACLCSR_RLPIEX_Msk (0x1U << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
#define ETH_MACLCSR_RLPIEN_Pos (2U)
#define ETH_MACLCSR_RLPIEN_Msk (0x1U << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
#define ETH_MACLCSR_TLPIEX_Pos (1U)
#define ETH_MACLCSR_TLPIEX_Msk (0x1U << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
#define ETH_MACLCSR_TLPIEN_Pos (0U)
#define ETH_MACLCSR_TLPIEN_Msk (0x1U << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
/* Bit definition for Ethernet MAC LPI Timers Control Register */
#define ETH_MACLTCR_LST_Pos (16U)
#define ETH_MACLTCR_LST_Msk (0x3FFU << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
#define ETH_MACLTCR_TWT_Pos (0U)
#define ETH_MACLTCR_TWT_Msk (0xFFFFU << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
/* Bit definition for Ethernet MAC LPI Entry Timer Register */
#define ETH_MACLETR_LPIET_Pos (0U)
#define ETH_MACLETR_LPIET_Msk (0xFFFFFU << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
/* Bit definition for Ethernet MAC 1US Tic Counter Register */
#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFU << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
/* Bit definition for Ethernet MAC Version Register */
#define ETH_MACVR_USERVER_Pos (8U)
#define ETH_MACVR_USERVER_Msk (0xFFU << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
#define ETH_MACVR_SNPSVER_Pos (0U)
#define ETH_MACVR_SNPSVER_Msk (0xFFU << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
/* Bit definition for Ethernet MAC Debug Register */
#define ETH_MACDR_TFCSTS_Pos (17U)
#define ETH_MACDR_TFCSTS_Msk (0x3U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1U << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1U << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3U << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
#define ETH_MACDR_TPESTS_Pos (16U)
#define ETH_MACDR_TPESTS_Msk (0x1U << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
#define ETH_MACDR_RFCFCSTS_Pos (1U)
#define ETH_MACDR_RFCFCSTS_Msk (0x3U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
#define ETH_MACDR_RPESTS_Pos (0U)
#define ETH_MACDR_RPESTS_Msk (0x1U << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
/* Bit definition for Ethernet MAC HW Feature0 Register */
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7U << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1U << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7U << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
#define ETH_MACHWF0R_SAVLANINS_Msk (0x1U << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3U << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1U << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1U << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3U << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1U << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64–127 Selected */
#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1U << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32–63 Selected */
#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FU << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1– 31 Selected */
#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
#define ETH_MACHWF0R_RXCOESEL_Msk (0x1U << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
#define ETH_MACHWF0R_TXCOESEL_Msk (0x1U << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
#define ETH_MACHWF0R_EEESEL_Pos (13U)
#define ETH_MACHWF0R_EEESEL_Msk (0x1U << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
#define ETH_MACHWF0R_TSSEL_Pos (12U)
#define ETH_MACHWF0R_TSSEL_Msk (0x1U << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1U << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
#define ETH_MACHWF0R_MMCSEL_Pos (8U)
#define ETH_MACHWF0R_MMCSEL_Msk (0x1U << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
#define ETH_MACHWF0R_MGKSEL_Pos (7U)
#define ETH_MACHWF0R_MGKSEL_Msk (0x1U << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
#define ETH_MACHWF0R_RWKSEL_Pos (6U)
#define ETH_MACHWF0R_RWKSEL_Msk (0x1U << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
#define ETH_MACHWF0R_SMASEL_Pos (5U)
#define ETH_MACHWF0R_SMASEL_Msk (0x1U << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
#define ETH_MACHWF0R_VLHASH_Pos (4U)
#define ETH_MACHWF0R_VLHASH_Msk (0x1U << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
#define ETH_MACHWF0R_PCSSEL_Pos (3U)
#define ETH_MACHWF0R_PCSSEL_Msk (0x1U << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
#define ETH_MACHWF0R_HDSEL_Pos (2U)
#define ETH_MACHWF0R_HDSEL_Msk (0x1U << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
#define ETH_MACHWF0R_GMIISEL_Pos (1U)
#define ETH_MACHWF0R_GMIISEL_Msk (0x1U << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
#define ETH_MACHWF0R_MIISEL_Pos (0U)
#define ETH_MACHWF0R_MIISEL_Msk (0x1U << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
/* Bit definition for Ethernet MAC HW Feature1 Register */
#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFU << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
#define ETH_MACHWF1R_AVSEL_Pos (20U)
#define ETH_MACHWF1R_AVSEL_Msk (0x1U << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
#define ETH_MACHWF1R_DBGMEMA_Msk (0x1U << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
#define ETH_MACHWF1R_TSOEN_Pos (18U)
#define ETH_MACHWF1R_TSOEN_Msk (0x1U << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
#define ETH_MACHWF1R_SPHEN_Pos (17U)
#define ETH_MACHWF1R_SPHEN_Msk (0x1U << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
#define ETH_MACHWF1R_DCBEN_Pos (16U)
#define ETH_MACHWF1R_DCBEN_Msk (0x1U << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
#define ETH_MACHWF1R_ADDR64_Pos (14U)
#define ETH_MACHWF1R_ADDR64_Msk (0x3U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
#define ETH_MACHWF1R_ADDR64_32 (0x0U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
#define ETH_MACHWF1R_ADDR64_40 (0x1U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
#define ETH_MACHWF1R_ADDR64_48 (0x2U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1U << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
#define ETH_MACHWF1R_PTOEN_Pos (12U)
#define ETH_MACHWF1R_PTOEN_Msk (0x1U << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
#define ETH_MACHWF1R_OSTEN_Pos (11U)
#define ETH_MACHWF1R_OSTEN_Msk (0x1U << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
/* Bit definition for Ethernet MAC HW Feature2 Register */
#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
#define ETH_MACHWF2R_TXCHCNT_Msk (0xFU << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
#define ETH_MACHWF2R_RXCHCNT_Msk (0x7U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
#define ETH_MACHWF2R_TXQCNT_Pos (6U)
#define ETH_MACHWF2R_TXQCNT_Msk (0xFU << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
#define ETH_MACHWF2R_RXQCNT_Pos (0U)
#define ETH_MACHWF2R_RXQCNT_Msk (0xFU << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
/* Bit definition for Ethernet MAC MDIO Address Register */
#define ETH_MACMDIOAR_PSE_Pos (27U)
#define ETH_MACMDIOAR_PSE_Msk (0x1U << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
#define ETH_MACMDIOAR_BTB_Pos (26U)
#define ETH_MACMDIOAR_BTB_Msk (0x1U << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
#define ETH_MACMDIOAR_PA_Pos (21U)
#define ETH_MACMDIOAR_PA_Msk (0x1FU << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
#define ETH_MACMDIOAR_RDA_Pos (16U)
#define ETH_MACMDIOAR_RDA_Msk (0x1FU << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
#define ETH_MACMDIOAR_NTC_Pos (12U)
#define ETH_MACMDIOAR_NTC_Msk (0x7U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
#define ETH_MACMDIOAR_CR_Pos (8U)
#define ETH_MACMDIOAR_CR_Msk (0xFU << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1U << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1U << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3U << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1U << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5U << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1U << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9U << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5U << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBU << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3U << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDU << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7U << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFU << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_SKAP_Pos (4U)
#define ETH_MACMDIOAR_SKAP_Msk (0x1U << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
#define ETH_MACMDIOAR_MOC_Pos (2U)
#define ETH_MACMDIOAR_MOC_Msk (0x3U << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
#define ETH_MACMDIOAR_MOC_WR_Msk (0x1U << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1U << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
#define ETH_MACMDIOAR_MOC_RD_Msk (0x3U << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
#define ETH_MACMDIOAR_C45E_Pos (1U)
#define ETH_MACMDIOAR_C45E_Msk (0x1U << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
#define ETH_MACMDIOAR_MB_Pos (0U)
#define ETH_MACMDIOAR_MB_Msk (0x1U << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
/* Bit definition for Ethernet MAC MDIO Data Register */
#define ETH_MACMDIODR_RA_Pos (16U)
#define ETH_MACMDIODR_RA_Msk (0xFFFFU << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
#define ETH_MACMDIODR_MD_Pos (0U)
#define ETH_MACMDIODR_MD_Msk (0xFFFFU << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
/* Bit definition for Ethernet MAC Address High Register */
#define ETH_MACAHR_AE_Pos (31U)
#define ETH_MACAHR_AE_Msk (0x1U << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
#define ETH_MACAHR_SA_Pos (30U)
#define ETH_MACAHR_SA_Msk (0x1U << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
#define ETH_MACAHR_MBC_Pos (24U)
#define ETH_MACAHR_MBC_Msk (0x3FU << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACAHR_MACAH_Pos (0U)
#define ETH_MACAHR_MACAH_Msk (0xFFFFU << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
/* Bit definition for Ethernet MAC Address Low Register */
#define ETH_MACALR_MACAL_Pos (0U)
#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFU << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
/* Bit definition for Ethernet MAC L3 L4 Control Register */
#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
#define ETH_MACL3L4CR_L4DPIM_Msk (0x1U << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
#define ETH_MACL3L4CR_L4DPM_Pos (20U)
#define ETH_MACL3L4CR_L4DPM_Msk (0x1U << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
#define ETH_MACL3L4CR_L4SPIM_Msk (0x1U << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
#define ETH_MACL3L4CR_L4SPM_Pos (18U)
#define ETH_MACL3L4CR_L4SPM_Msk (0x1U << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
#define ETH_MACL3L4CR_L4PEN_Pos (16U)
#define ETH_MACL3L4CR_L4PEN_Msk (0x1U << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FU << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FU << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
#define ETH_MACL3L4CR_L3DAIM_Msk (0x1U << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
#define ETH_MACL3L4CR_L3DAM_Pos (4U)
#define ETH_MACL3L4CR_L3DAM_Msk (0x1U << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
#define ETH_MACL3L4CR_L3SAIM_Msk (0x1U << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
#define ETH_MACL3L4CR_L3SAM_Pos (2U)
#define ETH_MACL3L4CR_L3SAM_Msk (0x1U << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
#define ETH_MACL3L4CR_L3PEN_Pos (0U)
#define ETH_MACL3L4CR_L3PEN_Msk (0x1U << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
/* Bit definition for Ethernet MAC L4 Address Register */
#define ETH_MACL4AR_L4DP_Pos (16U)
#define ETH_MACL4AR_L4DP_Msk (0xFFFFU << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
#define ETH_MACL4AR_L4SP_Pos (0U)
#define ETH_MACL4AR_L4SP_Msk (0xFFFFU << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
/* Bit definition for Ethernet MAC L3 Address0 Register */
#define ETH_MACL3A0R_L3A0_Pos (0U)
#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFU << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
/* Bit definition for Ethernet MAC L4 Address1 Register */
#define ETH_MACL3A1R_L3A1_Pos (0U)
#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFU << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
/* Bit definition for Ethernet MAC L4 Address2 Register */
#define ETH_MACL3A2R_L3A2_Pos (0U)
#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFU << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
/* Bit definition for Ethernet MAC L4 Address3 Register */
#define ETH_MACL3A3R_L3A3_Pos (0U)
#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFU << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
/* Bit definition for Ethernet MTL Operation Mode Register */
#define ETH_MTLOMR_CNTCLR_Pos (9U)
#define ETH_MTLOMR_CNTCLR_Msk (0x1U << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
#define ETH_MTLOMR_CNTPRST_Pos (8U)
#define ETH_MTLOMR_CNTPRST_Msk (0x1U << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
/* Bit definition for Ethernet MTL Interrupt Status Register */
#define ETH_MTLISR_MACIS_Pos (16U)
#define ETH_MTLISR_MACIS_Msk (0x1U << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
#define ETH_MTLISR_QIS_Pos (0U)
#define ETH_MTLISR_QIS_Msk (0x1U << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
#define ETH_MTLTQOMR_TTC_Pos (4U)
#define ETH_MTLTQOMR_TTC_Msk (0x7U << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
#define ETH_MTLTQOMR_TSF_Pos (1U)
#define ETH_MTLTQOMR_TSF_Msk (0x1U << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
#define ETH_MTLTQOMR_FTQ_Pos (0U)
#define ETH_MTLTQOMR_FTQ_Msk (0x1U << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1U << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFU << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
/* Bit definition for Ethernet MTL Tx Queue Debug Register */
#define ETH_MTLTQDR_STXSTSF_Pos (20U)
#define ETH_MTLTQDR_STXSTSF_Msk (0x7U << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
#define ETH_MTLTQDR_PTXQ_Pos (16U)
#define ETH_MTLTQDR_PTXQ_Msk (0x7U << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1U << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
#define ETH_MTLTQDR_TXQSTS_Pos (4U)
#define ETH_MTLTQDR_TXQSTS_Msk (0x1U << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
#define ETH_MTLTQDR_TWCSTS_Pos (3U)
#define ETH_MTLTQDR_TWCSTS_Msk (0x1U << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
#define ETH_MTLTQDR_TRCSTS_Msk (0x3U << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
#define ETH_MTLTQDR_TXQSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MTLTQDR_TXQSTS_READ_Pos (1U)
#define ETH_MTLTQDR_TXQSTS_READ_Msk (0x1U << ETH_MTLTQDR_TXQSTS_READ_Pos) /*!< 0x00000002 */
#define ETH_MTLTQDR_TXQSTS_READ ETH_MTLTQDR_TXQSTS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
#define ETH_MTLTQDR_TXQSTS_WAITING_Pos (2U)
#define ETH_MTLTQDR_TXQSTS_WAITING_Msk (0x1U << ETH_MTLTQDR_TXQSTS_WAITING_Pos) /*!< 0x00000004 */
#define ETH_MTLTQDR_TXQSTS_WAITING ETH_MTLTQDR_TXQSTS_WAITING_Msk /* Waiting for pending Tx Status from the MAC transmitter */
#define ETH_MTLTQDR_TXQSTS_FLUSHING_Pos (1U)
#define ETH_MTLTQDR_TXQSTS_FLUSHING_Msk (0x3U << ETH_MTLTQDR_TXQSTS_FLUSHING_Pos) /*!< 0x00000006 */
#define ETH_MTLTQDR_TXQSTS_FLUSHING ETH_MTLTQDR_TXQSTS_FLUSHING_Msk /* Flushing the Tx queue because of the Packet Abort request from the MAC */
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1U << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
#define ETH_MTLQICSR_RXOIE_Pos (24U)
#define ETH_MTLQICSR_RXOIE_Msk (0x1U << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
#define ETH_MTLQICSR_RXOVFIS_Msk (0x1U << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
#define ETH_MTLQICSR_TXUIE_Pos (8U)
#define ETH_MTLQICSR_TXUIE_Msk (0x1U << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
#define ETH_MTLQICSR_TXUNFIS_Msk (0x1U << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1U << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
#define ETH_MTLRQOMR_RSF_Pos (5U)
#define ETH_MTLRQOMR_RSF_Msk (0x1U << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
#define ETH_MTLRQOMR_FEP_Pos (4U)
#define ETH_MTLRQOMR_FEP_Msk (0x1U << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
#define ETH_MTLRQOMR_FUP_Pos (3U)
#define ETH_MTLRQOMR_FUP_Msk (0x1U << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
#define ETH_MTLRQOMR_RTC_Pos (0U)
#define ETH_MTLRQOMR_RTC_Msk (0x3U << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1U << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFU << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1U << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFU << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
/* Bit definition for Ethernet MTL Rx Queue Debug Register */
#define ETH_MTLRQDR_PRXQ_Pos (16U)
#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFU << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
#define ETH_MTLRQDR_RXQSTS_Msk (0x3U << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1U << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1U << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3U << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
#define ETH_MTLRQDR_RRCSTS_Msk (0x3U << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1U << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1U << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3U << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
#define ETH_MTLRQDR_RWCSTS_Pos (0U)
#define ETH_MTLRQDR_RWCSTS_Msk (0x1U << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
/* Bit definition for Ethernet MTL Rx Queue Control Register */
#define ETH_MTLRQCR_RQPA_Pos (3U)
#define ETH_MTLRQCR_RQPA_Msk (0x1U << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
#define ETH_MTLRQCR_RQW_Pos (0U)
#define ETH_MTLRQCR_RQW_Msk (0x7U << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
/* Bit definition for Ethernet DMA Mode Register */
#define ETH_DMAMR_INTM_Pos (16U)
#define ETH_DMAMR_INTM_Msk (0x3U << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
#define ETH_DMAMR_INTM_0 (0x0U << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
#define ETH_DMAMR_INTM_1 (0x1U << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
#define ETH_DMAMR_INTM_2 (0x2U << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
#define ETH_DMAMR_PR_Pos (12U)
#define ETH_DMAMR_PR_Msk (0x7U << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
#define ETH_DMAMR_TXPR_Pos (11U)
#define ETH_DMAMR_TXPR_Msk (0x1U << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
#define ETH_DMAMR_DA_Pos (1U)
#define ETH_DMAMR_DA_Msk (0x1U << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
#define ETH_DMAMR_SWR_Pos (0U)
#define ETH_DMAMR_SWR_Msk (0x1U << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
/* Bit definition for Ethernet DMA SysBus Mode Register */
#define ETH_DMASBMR_RB_Pos (15U)
#define ETH_DMASBMR_RB_Msk (0x1U << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
#define ETH_DMASBMR_MB_Pos (14U)
#define ETH_DMASBMR_MB_Msk (0x1U << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
#define ETH_DMASBMR_AAL_Pos (12U)
#define ETH_DMASBMR_AAL_Msk (0x1U << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
#define ETH_DMASBMR_FB_Pos (0U)
#define ETH_DMASBMR_FB_Msk (0x1U << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
/* Bit definition for Ethernet DMA Interrupt Status Register */
#define ETH_DMAISR_MACIS_Pos (17U)
#define ETH_DMAISR_MACIS_Msk (0x1U << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
#define ETH_DMAISR_MTLIS_Pos (16U)
#define ETH_DMAISR_MTLIS_Msk (0x1U << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
#define ETH_DMAISR_DMACIS_Pos (0U)
#define ETH_DMAISR_DMACIS_Msk (0x1U << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
/* Bit definition for Ethernet DMA Debug Status Register */
#define ETH_DMADSR_TPS_Pos (12U)
#define ETH_DMADSR_TPS_Msk (0xFU << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1U << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
#define ETH_DMADSR_TPS_WAITING_Pos (13U)
#define ETH_DMADSR_TPS_WAITING_Msk (0x1U << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_TPS_READING_Pos (12U)
#define ETH_DMADSR_TPS_READING_Msk (0x3U << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1U << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3U << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
#define ETH_DMADSR_TPS_CLOSING_Msk (0x7U << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
#define ETH_DMADSR_RPS_Pos (8U)
#define ETH_DMADSR_RPS_Msk (0xFU << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1U << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
#define ETH_DMADSR_RPS_WAITING_Pos (12U)
#define ETH_DMADSR_RPS_WAITING_Msk (0x3U << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1U << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
#define ETH_DMADSR_RPS_CLOSING_Msk (0x5U << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3U << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7U << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
/* Bit definition for Ethernet DMA Channel Control Register */
#define ETH_DMACCR_DSL_Pos (18U)
#define ETH_DMACCR_DSL_Msk (0x7U << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
#define ETH_DMACCR_MSS_Pos (0U)
#define ETH_DMACCR_MSS_Msk (0x3FFFU << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
/* Bit definition for Ethernet DMA Channel Tx Control Register */
#define ETH_DMACTCR_TPBL_Pos (16U)
#define ETH_DMACTCR_TPBL_Msk (0x3FU << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
#define ETH_DMACTCR_TSE_Pos (12U)
#define ETH_DMACTCR_TSE_Msk (0x1U << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
#define ETH_DMACTCR_OSP_Pos (4U)
#define ETH_DMACTCR_OSP_Msk (0x1U << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
#define ETH_DMACTCR_ST_Pos (0U)
#define ETH_DMACTCR_ST_Msk (0x1U << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
/* Bit definition for Ethernet DMA Channel Rx Control Register */
#define ETH_DMACRCR_RPF_Pos (31U)
#define ETH_DMACRCR_RPF_Msk (0x1U << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
#define ETH_DMACRCR_RPBL_Pos (16U)
#define ETH_DMACRCR_RPBL_Msk (0x3FU << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
#define ETH_DMACRCR_RBSZ_Pos (1U)
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFU << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
#define ETH_DMACRCR_SR_Pos (0U)
#define ETH_DMACRCR_SR_Msk (0x1U << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
#define ETH_DMACTDLAR_TDESLA_Pos (2U)
#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFU << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
#define ETH_DMACRDLAR_RDESLA_Pos (2U)
#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFU << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
#define ETH_DMACTDTPR_TDT_Pos (2U)
#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFU << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
#define ETH_DMACRDTPR_RDT_Pos (2U)
#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFU << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
#define ETH_DMACTDRLR_TDRL_Pos (0U)
#define ETH_DMACTDRLR_TDRL_Msk (0x3FFU << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
#define ETH_DMACRDRLR_RDRL_Pos (0U)
#define ETH_DMACRDRLR_RDRL_Msk (0x3FFU << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
#define ETH_DMACIER_NIE_Pos (15U)
#define ETH_DMACIER_NIE_Msk (0x1U << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
#define ETH_DMACIER_AIE_Pos (14U)
#define ETH_DMACIER_AIE_Msk (0x1U << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
#define ETH_DMACIER_CDEE_Pos (13U)
#define ETH_DMACIER_CDEE_Msk (0x1U << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
#define ETH_DMACIER_FBEE_Pos (12U)
#define ETH_DMACIER_FBEE_Msk (0x1U << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
#define ETH_DMACIER_ERIE_Pos (11U)
#define ETH_DMACIER_ERIE_Msk (0x1U << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
#define ETH_DMACIER_ETIE_Pos (10U)
#define ETH_DMACIER_ETIE_Msk (0x1U << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
#define ETH_DMACIER_RWTE_Pos (9U)
#define ETH_DMACIER_RWTE_Msk (0x1U << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
#define ETH_DMACIER_RSE_Pos (8U)
#define ETH_DMACIER_RSE_Msk (0x1U << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
#define ETH_DMACIER_RBUE_Pos (7U)
#define ETH_DMACIER_RBUE_Msk (0x1U << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
#define ETH_DMACIER_RIE_Pos (6U)
#define ETH_DMACIER_RIE_Msk (0x1U << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
#define ETH_DMACIER_TBUE_Pos (2U)
#define ETH_DMACIER_TBUE_Msk (0x1U << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
#define ETH_DMACIER_TXSE_Pos (1U)
#define ETH_DMACIER_TXSE_Msk (0x1U << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
#define ETH_DMACIER_TIE_Pos (0U)
#define ETH_DMACIER_TIE_Msk (0x1U << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
#define ETH_DMACRIWTR_RWT_Pos (0U)
#define ETH_DMACRIWTR_RWT_Msk (0xFFU << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFU << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
/* Bit definition for Ethernet DMA Channel Status Register */
#define ETH_DMACSR_REB_Pos (19U)
#define ETH_DMACSR_REB_Msk (0x7U << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
#define ETH_DMACSR_TEB_Pos (16U)
#define ETH_DMACSR_TEB_Msk (0x7U << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
#define ETH_DMACSR_NIS_Pos (15U)
#define ETH_DMACSR_NIS_Msk (0x1U << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
#define ETH_DMACSR_AIS_Pos (14U)
#define ETH_DMACSR_AIS_Msk (0x1U << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
#define ETH_DMACSR_CDE_Pos (13U)
#define ETH_DMACSR_CDE_Msk (0x1U << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
#define ETH_DMACSR_FBE_Pos (12U)
#define ETH_DMACSR_FBE_Msk (0x1U << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
#define ETH_DMACSR_ERI_Pos (11U)
#define ETH_DMACSR_ERI_Msk (0x1U << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
#define ETH_DMACSR_ETI_Pos (10U)
#define ETH_DMACSR_ETI_Msk (0x1U << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
#define ETH_DMACSR_RWT_Pos (9U)
#define ETH_DMACSR_RWT_Msk (0x1U << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
#define ETH_DMACSR_RPS_Pos (8U)
#define ETH_DMACSR_RPS_Msk (0x1U << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
#define ETH_DMACSR_RBU_Pos (7U)
#define ETH_DMACSR_RBU_Msk (0x1U << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
#define ETH_DMACSR_RI_Pos (6U)
#define ETH_DMACSR_RI_Msk (0x1U << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
#define ETH_DMACSR_TBU_Pos (2U)
#define ETH_DMACSR_TBU_Msk (0x1U << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
#define ETH_DMACSR_TPS_Pos (1U)
#define ETH_DMACSR_TPS_Msk (0x1U << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
#define ETH_DMACSR_TI_Pos (0U)
#define ETH_DMACSR_TI_Msk (0x1U << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
/* Bit definition for Ethernet DMA Channel missed frame count register */
#define ETH_DMACMFCR_MFCO_Pos (15U)
#define ETH_DMACMFCR_MFCO_Msk (0x1U << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
#define ETH_DMACMFCR_MFC_Pos (0U)
#define ETH_DMACMFCR_MFC_Msk (0x7FFU << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_MBURST_Pos (23U)
#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
#define DMA_SxCR_PBURST_Pos (21U)
#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
#define DMA_SxCR_DBM_Pos (18U)
#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
#define DMA_SxCR_PL_Pos (16U)
#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
#define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
#define DMA_SxCR_PINCOS_Pos (15U)
#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
#define DMA_SxCR_MSIZE_Pos (13U)
#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
#define DMA_SxCR_PSIZE_Pos (11U)
#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
#define DMA_SxCR_MINC_Pos (10U)
#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
#define DMA_SxCR_PINC_Pos (9U)
#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_SxCR_CIRC_Pos (8U)
#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
#define DMA_SxCR_DIR_Pos (6U)
#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
#define DMA_SxCR_PFCTRL_Pos (5U)
#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
#define DMA_SxCR_TCIE_Pos (4U)
#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_SxCR_HTIE_Pos (3U)
#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
#define DMA_SxCR_TEIE_Pos (2U)
#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_SxCR_DMEIE_Pos (1U)
#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
#define DMA_SxCR_EN_Pos (0U)
#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
#define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT_Pos (0U)
#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
#define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE_Pos (7U)
#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
#define DMA_SxFCR_FS_Pos (3U)
#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
#define DMA_SxFCR_DMDIS_Pos (2U)
#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
#define DMA_SxFCR_FTH_Pos (0U)
#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3_Pos (27U)
#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
#define DMA_LISR_HTIF3_Pos (26U)
#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
#define DMA_LISR_TEIF3_Pos (25U)
#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
#define DMA_LISR_DMEIF3_Pos (24U)
#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
#define DMA_LISR_FEIF3_Pos (22U)
#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
#define DMA_LISR_TCIF2_Pos (21U)
#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
#define DMA_LISR_HTIF2_Pos (20U)
#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
#define DMA_LISR_TEIF2_Pos (19U)
#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
#define DMA_LISR_DMEIF2_Pos (18U)
#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
#define DMA_LISR_FEIF2_Pos (16U)
#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
#define DMA_LISR_TCIF1_Pos (11U)
#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
#define DMA_LISR_HTIF1_Pos (10U)
#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
#define DMA_LISR_TEIF1_Pos (9U)
#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
#define DMA_LISR_DMEIF1_Pos (8U)
#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
#define DMA_LISR_FEIF1_Pos (6U)
#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
#define DMA_LISR_TCIF0_Pos (5U)
#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
#define DMA_LISR_HTIF0_Pos (4U)
#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
#define DMA_LISR_TEIF0_Pos (3U)
#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
#define DMA_LISR_DMEIF0_Pos (2U)
#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
#define DMA_LISR_FEIF0_Pos (0U)
#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7_Pos (27U)
#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
#define DMA_HISR_HTIF7_Pos (26U)
#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
#define DMA_HISR_TEIF7_Pos (25U)
#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
#define DMA_HISR_DMEIF7_Pos (24U)
#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
#define DMA_HISR_FEIF7_Pos (22U)
#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
#define DMA_HISR_TCIF6_Pos (21U)
#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
#define DMA_HISR_HTIF6_Pos (20U)
#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
#define DMA_HISR_TEIF6_Pos (19U)
#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
#define DMA_HISR_DMEIF6_Pos (18U)
#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
#define DMA_HISR_FEIF6_Pos (16U)
#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
#define DMA_HISR_TCIF5_Pos (11U)
#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
#define DMA_HISR_HTIF5_Pos (10U)
#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
#define DMA_HISR_TEIF5_Pos (9U)
#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
#define DMA_HISR_DMEIF5_Pos (8U)
#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
#define DMA_HISR_FEIF5_Pos (6U)
#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
#define DMA_HISR_TCIF4_Pos (5U)
#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
#define DMA_HISR_HTIF4_Pos (4U)
#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
#define DMA_HISR_TEIF4_Pos (3U)
#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
#define DMA_HISR_DMEIF4_Pos (2U)
#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
#define DMA_HISR_FEIF4_Pos (0U)
#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3_Pos (27U)
#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
#define DMA_LIFCR_CHTIF3_Pos (26U)
#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
#define DMA_LIFCR_CTEIF3_Pos (25U)
#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
#define DMA_LIFCR_CDMEIF3_Pos (24U)
#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
#define DMA_LIFCR_CFEIF3_Pos (22U)
#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
#define DMA_LIFCR_CTCIF2_Pos (21U)
#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
#define DMA_LIFCR_CHTIF2_Pos (20U)
#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
#define DMA_LIFCR_CTEIF2_Pos (19U)
#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
#define DMA_LIFCR_CDMEIF2_Pos (18U)
#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
#define DMA_LIFCR_CFEIF2_Pos (16U)
#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
#define DMA_LIFCR_CTCIF1_Pos (11U)
#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
#define DMA_LIFCR_CHTIF1_Pos (10U)
#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
#define DMA_LIFCR_CTEIF1_Pos (9U)
#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
#define DMA_LIFCR_CDMEIF1_Pos (8U)
#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
#define DMA_LIFCR_CFEIF1_Pos (6U)
#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
#define DMA_LIFCR_CTCIF0_Pos (5U)
#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
#define DMA_LIFCR_CHTIF0_Pos (4U)
#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
#define DMA_LIFCR_CTEIF0_Pos (3U)
#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
#define DMA_LIFCR_CDMEIF0_Pos (2U)
#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
#define DMA_LIFCR_CFEIF0_Pos (0U)
#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7_Pos (27U)
#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
#define DMA_HIFCR_CHTIF7_Pos (26U)
#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
#define DMA_HIFCR_CTEIF7_Pos (25U)
#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
#define DMA_HIFCR_CDMEIF7_Pos (24U)
#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
#define DMA_HIFCR_CFEIF7_Pos (22U)
#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
#define DMA_HIFCR_CTCIF6_Pos (21U)
#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
#define DMA_HIFCR_CHTIF6_Pos (20U)
#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
#define DMA_HIFCR_CTEIF6_Pos (19U)
#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
#define DMA_HIFCR_CDMEIF6_Pos (18U)
#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
#define DMA_HIFCR_CFEIF6_Pos (16U)
#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
#define DMA_HIFCR_CTCIF5_Pos (11U)
#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
#define DMA_HIFCR_CHTIF5_Pos (10U)
#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
#define DMA_HIFCR_CTEIF5_Pos (9U)
#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
#define DMA_HIFCR_CDMEIF5_Pos (8U)
#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
#define DMA_HIFCR_CFEIF5_Pos (6U)
#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
#define DMA_HIFCR_CTCIF4_Pos (5U)
#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
#define DMA_HIFCR_CHTIF4_Pos (4U)
#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
#define DMA_HIFCR_CTEIF4_Pos (3U)
#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
#define DMA_HIFCR_CDMEIF4_Pos (2U)
#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
#define DMA_HIFCR_CFEIF4_Pos (0U)
#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
/****************** Bit definition for DMA_SxPAR register ********************/
#define DMA_SxPAR_PA_Pos (0U)
#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_SxM0AR register ********************/
#define DMA_SxM0AR_M0A_Pos (0U)
#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
/****************** Bit definition for DMA_SxM1AR register ********************/
#define DMA_SxM1AR_M1A_Pos (0U)
#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register **************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1U << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1U << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
/******************** Bits definition for DMAMUX_CFR register **************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1U << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1U << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_RGxCR_NBREQ_Pos (19U)
#define DMAMUX_RGxCR_NBREQ_Msk (0x1FU << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_RGxCR_NBREQ DMAMUX_RGxCR_NBREQ_Msk /*!< Number of DMA requests to be generated */
#define DMAMUX_RGxCR_NBREQ_0 (0x01U << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_RGxCR_NBREQ_1 (0x02U << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_RGxCR_NBREQ_2 (0x04U << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_RGxCR_NBREQ_3 (0x08U << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_RGxCR_NBREQ_4 (0x10U << DMAMUX_RGxCR_NBREQ_Pos) /*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
#define DMAMUX_RGSR_OF4_Pos (4U)
#define DMAMUX_RGSR_OF4_Msk (0x1U << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
#define DMAMUX_RGSR_OF5_Pos (5U)
#define DMAMUX_RGSR_OF5_Msk (0x1U << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
#define DMAMUX_RGSR_OF6_Pos (6U)
#define DMAMUX_RGSR_OF6_Msk (0x1U << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
#define DMAMUX_RGSR_OF7_Pos (7U)
#define DMAMUX_RGSR_OF7_Msk (0x1U << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
/******************** Bits definition for DMAMUX_RGCFR register **************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF4_Pos (4U)
#define DMAMUX_RGCFR_COF4_Msk (0x1U << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF5_Pos (5U)
#define DMAMUX_RGCFR_COF5_Msk (0x1U << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF6_Pos (6U)
#define DMAMUX_RGCFR_COF6_Msk (0x1U << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
#define DMAMUX_RGCFR_COF7_Pos (7U)
#define DMAMUX_RGCFR_COF7_Msk (0x1U << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
/******************************************************************************/
/* */
/* AHB Master DMA2D Controller (DMA2D) */
/* */
/******************************************************************************/
/******************** Bit definition for DMA2D_CR register ******************/
#define DMA2D_CR_START_Pos (0U)
#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
#define DMA2D_CR_SUSP_Pos (1U)
#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
#define DMA2D_CR_ABORT_Pos (2U)
#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
#define DMA2D_CR_TEIE_Pos (8U)
#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE_Pos (9U)
#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE_Pos (10U)
#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE_Pos (11U)
#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE_Pos (12U)
#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE_Pos (13U)
#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE_Pos (16U)
#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
/******************** Bit definition for DMA2D_ISR register *****************/
#define DMA2D_ISR_TEIF_Pos (0U)
#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF_Pos (1U)
#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF_Pos (2U)
#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF_Pos (3U)
#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF_Pos (4U)
#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF_Pos (5U)
#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_IFCR register ****************/
#define DMA2D_IFCR_CTEIF_Pos (0U)
#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFCR_CTCIF_Pos (1U)
#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CTWIF_Pos (2U)
#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFCR_CAECIF_Pos (3U)
#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFCR_CCTCIF_Pos (4U)
#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CCEIF_Pos (5U)
#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_FGMAR register ***************/
#define DMA2D_FGMAR_MA_Pos (0U)
#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
/******************** Bit definition for DMA2D_FGOR register ****************/
#define DMA2D_FGOR_LO_Pos (0U)
#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_BGMAR register ***************/
#define DMA2D_BGMAR_MA_Pos (0U)
#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
/******************** Bit definition for DMA2D_BGOR register ****************/
#define DMA2D_BGOR_LO_Pos (0U)
#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_FGPFCCR register *************/
#define DMA2D_FGPFCCR_CM_Pos (0U)
#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_FGPFCCR_CCM_Pos (4U)
#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START_Pos (5U)
#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
#define DMA2D_FGPFCCR_CS_Pos (8U)
#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_FGPFCCR_AM_Pos (16U)
#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_FGPFCCR_CSS_Pos (18U)
#define DMA2D_FGPFCCR_CSS_Msk (0x3U << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
#define DMA2D_FGPFCCR_CSS_0 (0x1U << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
#define DMA2D_FGPFCCR_CSS_1 (0x2U << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
#define DMA2D_FGPFCCR_AI_Pos (20U)
#define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
#define DMA2D_FGPFCCR_RBS_Pos (21U)
#define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
/******************** Bit definition for DMA2D_FGCOLR register **************/
#define DMA2D_FGCOLR_BLUE_Pos (0U)
#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
#define DMA2D_FGCOLR_GREEN_Pos (8U)
#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
#define DMA2D_FGCOLR_RED_Pos (16U)
#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
/******************** Bit definition for DMA2D_BGPFCCR register *************/
#define DMA2D_BGPFCCR_CM_Pos (0U)
#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_BGPFCCR_CM_3 (0x8U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_BGPFCCR_CCM_Pos (4U)
#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START_Pos (5U)
#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
#define DMA2D_BGPFCCR_CS_Pos (8U)
#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_BGPFCCR_AM_Pos (16U)
#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_BGPFCCR_AI_Pos (20U)
#define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
#define DMA2D_BGPFCCR_RBS_Pos (21U)
#define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
/******************** Bit definition for DMA2D_BGCOLR register **************/
#define DMA2D_BGCOLR_BLUE_Pos (0U)
#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
#define DMA2D_BGCOLR_GREEN_Pos (8U)
#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
#define DMA2D_BGCOLR_RED_Pos (16U)
#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
/******************** Bit definition for DMA2D_FGCMAR register **************/
#define DMA2D_FGCMAR_MA_Pos (0U)
#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
/******************** Bit definition for DMA2D_BGCMAR register **************/
#define DMA2D_BGCMAR_MA_Pos (0U)
#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
/******************** Bit definition for DMA2D_OPFCCR register **************/
#define DMA2D_OPFCCR_CM_Pos (0U)
#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_OPFCCR_AI_Pos (20U)
#define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
#define DMA2D_OPFCCR_RBS_Pos (21U)
#define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
/******************** Bit definition for DMA2D_OCOLR register ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */
#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */
#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */
#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */
/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */
#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */
/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */
#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */
#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */
/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */
#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */
#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */
#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */
/******************** Bit definition for DMA2D_OMAR register ****************/
#define DMA2D_OMAR_MA_Pos (0U)
#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
/******************** Bit definition for DMA2D_OOR register *****************/
#define DMA2D_OOR_LO_Pos (0U)
#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
/******************** Bit definition for DMA2D_NLR register *****************/
#define DMA2D_NLR_NL_Pos (0U)
#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
#define DMA2D_NLR_PL_Pos (16U)
#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
/******************** Bit definition for DMA2D_LWR register *****************/
#define DMA2D_LWR_LW_Pos (0U)
#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
/******************** Bit definition for DMA2D_AMTCR register ***************/
#define DMA2D_AMTCR_EN_Pos (0U)
#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
#define DMA2D_AMTCR_DT_Pos (8U)
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register *******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
/******************* Bit definition for EXTI_IMR2 register *******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1U << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1U << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM43_Pos (11U)
#define EXTI_IMR2_IM43_Msk (0x1U << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
#define EXTI_IMR2_IM44_Pos (12U)
#define EXTI_IMR2_IM44_Msk (0x1U << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
#define EXTI_IMR2_IM45_Pos (13U)
#define EXTI_IMR2_IM45_Msk (0x1U << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
#define EXTI_IMR2_IM46_Pos (14U)
#define EXTI_IMR2_IM46_Msk (0x1U << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos (15U)
#define EXTI_IMR2_IM47_Msk (0x1U << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos (16U)
#define EXTI_IMR2_IM48_Msk (0x1U << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
#define EXTI_IMR2_IM49_Pos (17U)
#define EXTI_IMR2_IM49_Msk (0x1U << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
#define EXTI_IMR2_IM50_Pos (18U)
#define EXTI_IMR2_IM50_Msk (0x1U << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
#define EXTI_IMR2_IM51_Pos (19U)
#define EXTI_IMR2_IM51_Msk (0x1U << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
#define EXTI_IMR2_IM52_Pos (20U)
#define EXTI_IMR2_IM52_Msk (0x1U << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
#define EXTI_IMR2_IM53_Pos (21U)
#define EXTI_IMR2_IM53_Msk (0x1U << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
#define EXTI_IMR2_IM54_Pos (22U)
#define EXTI_IMR2_IM54_Msk (0x1U << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
#define EXTI_IMR2_IM55_Pos (23U)
#define EXTI_IMR2_IM55_Msk (0x1U << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
#define EXTI_IMR2_IM56_Pos (24U)
#define EXTI_IMR2_IM56_Msk (0x1U << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
#define EXTI_IMR2_IM57_Pos (25U)
#define EXTI_IMR2_IM57_Msk (0x1U << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
#define EXTI_IMR2_IM58_Pos (26U)
#define EXTI_IMR2_IM58_Msk (0x1U << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
#define EXTI_IMR2_IM59_Pos (27U)
#define EXTI_IMR2_IM59_Msk (0x1U << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
#define EXTI_IMR2_IM60_Pos (28U)
#define EXTI_IMR2_IM60_Msk (0x1U << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
#define EXTI_IMR2_IM61_Pos (29U)
#define EXTI_IMR2_IM61_Msk (0x1U << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
#define EXTI_IMR2_IM62_Pos (30U)
#define EXTI_IMR2_IM62_Msk (0x1U << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
#define EXTI_IMR2_IM63_Pos (31U)
#define EXTI_IMR2_IM63_Msk (0x1U << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
/******************* Bit definition for EXTI_IMR3 register *******************/
#define EXTI_IMR3_IM64_Pos (0U)
#define EXTI_IMR3_IM64_Msk (0x1U << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
#define EXTI_IMR3_IM65_Pos (1U)
#define EXTI_IMR3_IM65_Msk (0x1U << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
#define EXTI_IMR3_IM66_Pos (2U)
#define EXTI_IMR3_IM66_Msk (0x1U << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
#define EXTI_IMR3_IM67_Pos (3U)
#define EXTI_IMR3_IM67_Msk (0x1U << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
#define EXTI_IMR3_IM68_Pos (4U)
#define EXTI_IMR3_IM68_Msk (0x1U << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
#define EXTI_IMR3_IM69_Pos (5U)
#define EXTI_IMR3_IM69_Msk (0x1U << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
#define EXTI_IMR3_IM70_Pos (6U)
#define EXTI_IMR3_IM70_Msk (0x1U << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
#define EXTI_IMR3_IM71_Pos (7U)
#define EXTI_IMR3_IM71_Msk (0x1U << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
#define EXTI_IMR3_IM72_Pos (8U)
#define EXTI_IMR3_IM72_Msk (0x1U << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
#define EXTI_IMR3_IM73_Pos (9U)
#define EXTI_IMR3_IM73_Msk (0x1U << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
#define EXTI_IMR3_IM74_Pos (10U)
#define EXTI_IMR3_IM74_Msk (0x1U << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
#define EXTI_IMR3_IM75_Pos (11U)
#define EXTI_IMR3_IM75_Msk (0x1U << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
#define EXTI_IMR3_IM76_Pos (12U)
#define EXTI_IMR3_IM76_Msk (0x1U << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
#define EXTI_IMR3_IM77_Pos (13U)
#define EXTI_IMR3_IM77_Msk (0x1U << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
#define EXTI_IMR3_IM78_Pos (14U)
#define EXTI_IMR3_IM78_Msk (0x1U << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
#define EXTI_IMR3_IM79_Pos (15U)
#define EXTI_IMR3_IM79_Msk (0x1U << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
#define EXTI_IMR3_IM80_Pos (16U)
#define EXTI_IMR3_IM80_Msk (0x1U << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
#define EXTI_IMR3_IM81_Pos (17U)
#define EXTI_IMR3_IM81_Msk (0x1U << EXTI_IMR3_IM81_Pos) /*!< 0x00020000 */
#define EXTI_IMR3_IM81 EXTI_IMR3_IM81_Msk /*!< Interrupt Mask on line 81 */
#define EXTI_IMR3_IM82_Pos (18U)
#define EXTI_IMR3_IM82_Msk (0x1U << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
#define EXTI_IMR3_IM84_Pos (20U)
#define EXTI_IMR3_IM84_Msk (0x1U << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
#define EXTI_IMR3_IM85_Pos (21U)
#define EXTI_IMR3_IM85_Msk (0x1U << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
#define EXTI_IMR3_IM86_Pos (22U)
#define EXTI_IMR3_IM86_Msk (0x1U << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
#define EXTI_IMR3_IM87_Pos (23U)
#define EXTI_IMR3_IM87_Msk (0x1U << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
#define EXTI_IMR3_IM88_Pos (24U)
#define EXTI_IMR3_IM88_Msk (0x1U << EXTI_IMR3_IM88_Pos) /*!< 0x01000000 */
#define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk /*!< Interrupt Mask on line 88 */
/******************* Bit definition for EXTI_EMR1 register *******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_EMR2 register *******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1U << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1U << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM43_Pos (11U)
#define EXTI_EMR2_EM43_Msk (0x1U << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
#define EXTI_EMR2_EM44_Pos (12U)
#define EXTI_EMR2_EM44_Msk (0x1U << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
#define EXTI_EMR2_EM45_Pos (13U)
#define EXTI_EMR2_EM45_Msk (0x1U << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
#define EXTI_EMR2_EM46_Pos (14U)
#define EXTI_EMR2_EM46_Msk (0x1U << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
#define EXTI_EMR2_EM47_Pos (15U)
#define EXTI_EMR2_EM47_Msk (0x1U << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
#define EXTI_EMR2_EM48_Pos (16U)
#define EXTI_EMR2_EM48_Msk (0x1U << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
#define EXTI_EMR2_EM49_Pos (17U)
#define EXTI_EMR2_EM49_Msk (0x1U << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
#define EXTI_EMR2_EM50_Pos (18U)
#define EXTI_EMR2_EM50_Msk (0x1U << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
#define EXTI_EMR2_EM51_Pos (19U)
#define EXTI_EMR2_EM51_Msk (0x1U << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
#define EXTI_EMR2_EM52_Pos (20U)
#define EXTI_EMR2_EM52_Msk (0x1U << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
#define EXTI_EMR2_EM53_Pos (21U)
#define EXTI_EMR2_EM53_Msk (0x1U << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
#define EXTI_EMR2_EM54_Pos (22U)
#define EXTI_EMR2_EM54_Msk (0x1U << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
#define EXTI_EMR2_EM55_Pos (23U)
#define EXTI_EMR2_EM55_Msk (0x1U << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
#define EXTI_EMR2_EM56_Pos (24U)
#define EXTI_EMR2_EM56_Msk (0x1U << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
#define EXTI_EMR2_EM57_Pos (25U)
#define EXTI_EMR2_EM57_Msk (0x1U << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
#define EXTI_EMR2_EM58_Pos (26U)
#define EXTI_EMR2_EM58_Msk (0x1U << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
#define EXTI_EMR2_EM59_Pos (27U)
#define EXTI_EMR2_EM59_Msk (0x1U << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
#define EXTI_EMR2_EM60_Pos (28U)
#define EXTI_EMR2_EM60_Msk (0x1U << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
#define EXTI_EMR2_EM61_Pos (29U)
#define EXTI_EMR2_EM61_Msk (0x1U << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
#define EXTI_EMR2_EM62_Pos (30U)
#define EXTI_EMR2_EM62_Msk (0x1U << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
#define EXTI_EMR2_EM63_Pos (31U)
#define EXTI_EMR2_EM63_Msk (0x1U << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
/******************* Bit definition for EXTI_EMR3 register *******************/
#define EXTI_EMR3_EM64_Pos (0U)
#define EXTI_EMR3_EM64_Msk (0x1U << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
#define EXTI_EMR3_EM65_Pos (1U)
#define EXTI_EMR3_EM65_Msk (0x1U << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
#define EXTI_EMR3_EM66_Pos (2U)
#define EXTI_EMR3_EM66_Msk (0x1U << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
#define EXTI_EMR3_EM67_Pos (3U)
#define EXTI_EMR3_EM67_Msk (0x1U << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
#define EXTI_EMR3_EM68_Pos (4U)
#define EXTI_EMR3_EM68_Msk (0x1U << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
#define EXTI_EMR3_EM69_Pos (5U)
#define EXTI_EMR3_EM69_Msk (0x1U << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
#define EXTI_EMR3_EM70_Pos (6U)
#define EXTI_EMR3_EM70_Msk (0x1U << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
#define EXTI_EMR3_EM71_Pos (7U)
#define EXTI_EMR3_EM71_Msk (0x1U << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
#define EXTI_EMR3_EM72_Pos (8U)
#define EXTI_EMR3_EM72_Msk (0x1U << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
#define EXTI_EMR3_EM73_Pos (9U)
#define EXTI_EMR3_EM73_Msk (0x1U << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
#define EXTI_EMR3_EM74_Pos (10U)
#define EXTI_EMR3_EM74_Msk (0x1U << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
#define EXTI_EMR3_EM75_Pos (11U)
#define EXTI_EMR3_EM75_Msk (0x1U << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
#define EXTI_EMR3_EM76_Pos (12U)
#define EXTI_EMR3_EM76_Msk (0x1U << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
#define EXTI_EMR3_EM77_Pos (13U)
#define EXTI_EMR3_EM77_Msk (0x1U << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
#define EXTI_EMR3_EM78_Pos (14U)
#define EXTI_EMR3_EM78_Msk (0x1U << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
#define EXTI_EMR3_EM79_Pos (15U)
#define EXTI_EMR3_EM79_Msk (0x1U << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
#define EXTI_EMR3_EM80_Pos (16U)
#define EXTI_EMR3_EM80_Msk (0x1U << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
#define EXTI_EMR3_EM81_Pos (17U)
#define EXTI_EMR3_EM81_Msk (0x1U << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
#define EXTI_EMR3_EM82_Pos (18U)
#define EXTI_EMR3_EM82_Msk (0x1U << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
#define EXTI_EMR3_EM84_Pos (20U)
#define EXTI_EMR3_EM84_Msk (0x1U << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
#define EXTI_EMR3_EM85_Pos (21U)
#define EXTI_EMR3_EM85_Msk (0x1U << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
#define EXTI_EMR3_EM86_Pos (22U)
#define EXTI_EMR3_EM86_Msk (0x1U << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
#define EXTI_EMR3_EM87_Pos (23U)
#define EXTI_EMR3_EM87_Msk (0x1U << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
#define EXTI_EMR3_EM88_Pos (24U)
#define EXTI_EMR3_EM88_Msk (0x1U << EXTI_EMR3_EM88_Pos) /*!< 0x01000000 */
#define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk /*!< Event Mask on line 88 */
/****************** Bit definition for EXTI_RTSR1 register *******************/
#define EXTI_RTSR1_TR0_Pos (0U)
#define EXTI_RTSR1_TR0_Msk (0x1U << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_TR1_Pos (1U)
#define EXTI_RTSR1_TR1_Msk (0x1U << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_TR2_Pos (2U)
#define EXTI_RTSR1_TR2_Msk (0x1U << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_TR3_Pos (3U)
#define EXTI_RTSR1_TR3_Msk (0x1U << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_TR4_Pos (4U)
#define EXTI_RTSR1_TR4_Msk (0x1U << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_TR5_Pos (5U)
#define EXTI_RTSR1_TR5_Msk (0x1U << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_TR6_Pos (6U)
#define EXTI_RTSR1_TR6_Msk (0x1U << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_TR7_Pos (7U)
#define EXTI_RTSR1_TR7_Msk (0x1U << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_TR8_Pos (8U)
#define EXTI_RTSR1_TR8_Msk (0x1U << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_TR9_Pos (9U)
#define EXTI_RTSR1_TR9_Msk (0x1U << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_TR10_Pos (10U)
#define EXTI_RTSR1_TR10_Msk (0x1U << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_TR11_Pos (11U)
#define EXTI_RTSR1_TR11_Msk (0x1U << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_TR12_Pos (12U)
#define EXTI_RTSR1_TR12_Msk (0x1U << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_TR13_Pos (13U)
#define EXTI_RTSR1_TR13_Msk (0x1U << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_TR14_Pos (14U)
#define EXTI_RTSR1_TR14_Msk (0x1U << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_TR15_Pos (15U)
#define EXTI_RTSR1_TR15_Msk (0x1U << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_TR16_Pos (16U)
#define EXTI_RTSR1_TR16_Msk (0x1U << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_TR17_Pos (17U)
#define EXTI_RTSR1_TR17_Msk (0x1U << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_TR18_Pos (18U)
#define EXTI_RTSR1_TR18_Msk (0x1U << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR1_TR19_Pos (19U)
#define EXTI_RTSR1_TR19_Msk (0x1U << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_TR20_Pos (20U)
#define EXTI_RTSR1_TR20_Msk (0x1U << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_TR21_Pos (21U)
#define EXTI_RTSR1_TR21_Msk (0x1U << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
/****************** Bit definition for EXTI_RTSR2 register *******************/
#define EXTI_RTSR2_TR49_Pos (17U)
#define EXTI_RTSR2_TR49_Msk (0x1U << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
#define EXTI_RTSR2_TR51_Pos (19U)
#define EXTI_RTSR2_TR51_Msk (0x1U << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
/****************** Bit definition for EXTI_RTSR3 register *******************/
#define EXTI_RTSR3_TR82_Pos (18U)
#define EXTI_RTSR3_TR82_Msk (0x1U << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
#define EXTI_RTSR3_TR84_Pos (20U)
#define EXTI_RTSR3_TR84_Msk (0x1U << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
#define EXTI_RTSR3_TR85_Pos (21U)
#define EXTI_RTSR3_TR85_Msk (0x1U << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
#define EXTI_RTSR3_TR86_Pos (22U)
#define EXTI_RTSR3_TR86_Msk (0x1U << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
/****************** Bit definition for EXTI_FTSR1 register *******************/
#define EXTI_FTSR1_TR0_Pos (0U)
#define EXTI_FTSR1_TR0_Msk (0x1U << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_TR1_Pos (1U)
#define EXTI_FTSR1_TR1_Msk (0x1U << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_TR2_Pos (2U)
#define EXTI_FTSR1_TR2_Msk (0x1U << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_TR3_Pos (3U)
#define EXTI_FTSR1_TR3_Msk (0x1U << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_TR4_Pos (4U)
#define EXTI_FTSR1_TR4_Msk (0x1U << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_TR5_Pos (5U)
#define EXTI_FTSR1_TR5_Msk (0x1U << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_TR6_Pos (6U)
#define EXTI_FTSR1_TR6_Msk (0x1U << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_TR7_Pos (7U)
#define EXTI_FTSR1_TR7_Msk (0x1U << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_TR8_Pos (8U)
#define EXTI_FTSR1_TR8_Msk (0x1U << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_TR9_Pos (9U)
#define EXTI_FTSR1_TR9_Msk (0x1U << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_TR10_Pos (10U)
#define EXTI_FTSR1_TR10_Msk (0x1U << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_TR11_Pos (11U)
#define EXTI_FTSR1_TR11_Msk (0x1U << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_TR12_Pos (12U)
#define EXTI_FTSR1_TR12_Msk (0x1U << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_TR13_Pos (13U)
#define EXTI_FTSR1_TR13_Msk (0x1U << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_TR14_Pos (14U)
#define EXTI_FTSR1_TR14_Msk (0x1U << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_TR15_Pos (15U)
#define EXTI_FTSR1_TR15_Msk (0x1U << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_TR16_Pos (16U)
#define EXTI_FTSR1_TR16_Msk (0x1U << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_TR17_Pos (17U)
#define EXTI_FTSR1_TR17_Msk (0x1U << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_TR18_Pos (18U)
#define EXTI_FTSR1_TR18_Msk (0x1U << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR1_TR19_Pos (19U)
#define EXTI_FTSR1_TR19_Msk (0x1U << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_TR20_Pos (20U)
#define EXTI_FTSR1_TR20_Msk (0x1U << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_TR21_Pos (21U)
#define EXTI_FTSR1_TR21_Msk (0x1U << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
/****************** Bit definition for EXTI_FTSR2 register *******************/
#define EXTI_FTSR2_TR49_Pos (17U)
#define EXTI_FTSR2_TR49_Msk (0x1U << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
#define EXTI_FTSR2_TR51_Pos (19U)
#define EXTI_FTSR2_TR51_Msk (0x1U << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
/****************** Bit definition for EXTI_FTSR3 register *******************/
#define EXTI_FTSR3_TR82_Pos (18U)
#define EXTI_FTSR3_TR82_Msk (0x1U << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
#define EXTI_FTSR3_TR84_Pos (20U)
#define EXTI_FTSR3_TR84_Msk (0x1U << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
#define EXTI_FTSR3_TR85_Pos (21U)
#define EXTI_FTSR3_TR85_Msk (0x1U << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
#define EXTI_FTSR3_TR86_Pos (22U)
#define EXTI_FTSR3_TR86_Msk (0x1U << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
/****************** Bit definition for EXTI_SWIER1 register ******************/
#define EXTI_SWIER1_SWIER0_Pos (0U)
#define EXTI_SWIER1_SWIER0_Msk (0x1U << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWIER1_Pos (1U)
#define EXTI_SWIER1_SWIER1_Msk (0x1U << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWIER2_Pos (2U)
#define EXTI_SWIER1_SWIER2_Msk (0x1U << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWIER3_Pos (3U)
#define EXTI_SWIER1_SWIER3_Msk (0x1U << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWIER4_Pos (4U)
#define EXTI_SWIER1_SWIER4_Msk (0x1U << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWIER5_Pos (5U)
#define EXTI_SWIER1_SWIER5_Msk (0x1U << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWIER6_Pos (6U)
#define EXTI_SWIER1_SWIER6_Msk (0x1U << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWIER7_Pos (7U)
#define EXTI_SWIER1_SWIER7_Msk (0x1U << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWIER8_Pos (8U)
#define EXTI_SWIER1_SWIER8_Msk (0x1U << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWIER9_Pos (9U)
#define EXTI_SWIER1_SWIER9_Msk (0x1U << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWIER10_Pos (10U)
#define EXTI_SWIER1_SWIER10_Msk (0x1U << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWIER11_Pos (11U)
#define EXTI_SWIER1_SWIER11_Msk (0x1U << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWIER12_Pos (12U)
#define EXTI_SWIER1_SWIER12_Msk (0x1U << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWIER13_Pos (13U)
#define EXTI_SWIER1_SWIER13_Msk (0x1U << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWIER14_Pos (14U)
#define EXTI_SWIER1_SWIER14_Msk (0x1U << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWIER15_Pos (15U)
#define EXTI_SWIER1_SWIER15_Msk (0x1U << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWIER16_Pos (16U)
#define EXTI_SWIER1_SWIER16_Msk (0x1U << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWIER17_Pos (17U)
#define EXTI_SWIER1_SWIER17_Msk (0x1U << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWIER18_Pos (18U)
#define EXTI_SWIER1_SWIER18_Msk (0x1U << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER1_SWIER19_Pos (19U)
#define EXTI_SWIER1_SWIER19_Msk (0x1U << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWIER20_Pos (20U)
#define EXTI_SWIER1_SWIER20_Msk (0x1U << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWIER21_Pos (21U)
#define EXTI_SWIER1_SWIER21_Msk (0x1U << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
/****************** Bit definition for EXTI_SWIER2 register ******************/
#define EXTI_SWIER2_SWIER49_Pos (17U)
#define EXTI_SWIER2_SWIER49_Msk (0x1U << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
#define EXTI_SWIER2_SWIER51_Pos (19U)
#define EXTI_SWIER2_SWIER51_Msk (0x1U << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
/****************** Bit definition for EXTI_SWIER3 register ******************/
#define EXTI_SWIER3_SWIER82_Pos (18U)
#define EXTI_SWIER3_SWIER82_Msk (0x1U << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
#define EXTI_SWIER3_SWIER84_Pos (20U)
#define EXTI_SWIER3_SWIER84_Msk (0x1U << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
#define EXTI_SWIER3_SWIER85_Pos (21U)
#define EXTI_SWIER3_SWIER85_Msk (0x1U << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
#define EXTI_SWIER3_SWIER86_Pos (22U)
#define EXTI_SWIER3_SWIER86_Msk (0x1U << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
/****************** Bit definition for EXTI_D3PMR1 register ******************/
#define EXTI_D3PMR1_MR0_Pos (0U)
#define EXTI_D3PMR1_MR0_Msk (0x1U << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
#define EXTI_D3PMR1_MR1_Pos (1U)
#define EXTI_D3PMR1_MR1_Msk (0x1U << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
#define EXTI_D3PMR1_MR2_Pos (2U)
#define EXTI_D3PMR1_MR2_Msk (0x1U << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
#define EXTI_D3PMR1_MR3_Pos (3U)
#define EXTI_D3PMR1_MR3_Msk (0x1U << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
#define EXTI_D3PMR1_MR4_Pos (4U)
#define EXTI_D3PMR1_MR4_Msk (0x1U << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
#define EXTI_D3PMR1_MR5_Pos (5U)
#define EXTI_D3PMR1_MR5_Msk (0x1U << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
#define EXTI_D3PMR1_MR6_Pos (6U)
#define EXTI_D3PMR1_MR6_Msk (0x1U << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
#define EXTI_D3PMR1_MR7_Pos (7U)
#define EXTI_D3PMR1_MR7_Msk (0x1U << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
#define EXTI_D3PMR1_MR8_Pos (8U)
#define EXTI_D3PMR1_MR8_Msk (0x1U << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
#define EXTI_D3PMR1_MR9_Pos (9U)
#define EXTI_D3PMR1_MR9_Msk (0x1U << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
#define EXTI_D3PMR1_MR10_Pos (10U)
#define EXTI_D3PMR1_MR10_Msk (0x1U << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
#define EXTI_D3PMR1_MR11_Pos (11U)
#define EXTI_D3PMR1_MR11_Msk (0x1U << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
#define EXTI_D3PMR1_MR12_Pos (12U)
#define EXTI_D3PMR1_MR12_Msk (0x1U << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
#define EXTI_D3PMR1_MR13_Pos (13U)
#define EXTI_D3PMR1_MR13_Msk (0x1U << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
#define EXTI_D3PMR1_MR14_Pos (14U)
#define EXTI_D3PMR1_MR14_Msk (0x1U << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
#define EXTI_D3PMR1_MR15_Pos (15U)
#define EXTI_D3PMR1_MR15_Msk (0x1U << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
#define EXTI_D3PMR1_MR19_Pos (19U)
#define EXTI_D3PMR1_MR19_Msk (0x1U << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
#define EXTI_D3PMR1_MR20_Pos (20U)
#define EXTI_D3PMR1_MR20_Msk (0x1U << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
#define EXTI_D3PMR1_MR21_Pos (21U)
#define EXTI_D3PMR1_MR21_Msk (0x1U << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
#define EXTI_D3PMR1_MR25_Pos (24U)
#define EXTI_D3PMR1_MR25_Msk (0x1U << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
/****************** Bit definition for EXTI_D3PMR2 register ******************/
#define EXTI_D3PMR2_MR34_Pos (2U)
#define EXTI_D3PMR2_MR34_Msk (0x1U << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
#define EXTI_D3PMR2_MR35_Pos (3U)
#define EXTI_D3PMR2_MR35_Msk (0x1U << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
#define EXTI_D3PMR2_MR41_Pos (9U)
#define EXTI_D3PMR2_MR41_Msk (0x1U << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
#define EXTI_D3PMR2_MR48_Pos (16U)
#define EXTI_D3PMR2_MR48_Msk (0x1U << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
#define EXTI_D3PMR2_MR49_Pos (17U)
#define EXTI_D3PMR2_MR49_Msk (0x1U << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
#define EXTI_D3PMR2_MR50_Pos (18U)
#define EXTI_D3PMR2_MR50_Msk (0x1U << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
#define EXTI_D3PMR2_MR51_Pos (19U)
#define EXTI_D3PMR2_MR51_Msk (0x1U << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
#define EXTI_D3PMR2_MR52_Pos (20U)
#define EXTI_D3PMR2_MR52_Msk (0x1U << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
#define EXTI_D3PMR2_MR53_Pos (21U)
#define EXTI_D3PMR2_MR53_Msk (0x1U << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
/****************** Bit definition for EXTI_D3PMR3 register ******************/
#define EXTI_D3PMR3_MR88_Pos (24U)
#define EXTI_D3PMR3_MR88_Msk (0x1U << EXTI_D3PMR3_MR88_Pos) /*!< 0x01000000 */
#define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk /*!< Pending Mask Event for line 88 */
/******************* Bit definition for EXTI_PR1 register ********************/
#define EXTI_PR1_PR0_Pos (0U)
#define EXTI_PR1_PR0_Msk (0x1U << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PR1_Pos (1U)
#define EXTI_PR1_PR1_Msk (0x1U << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PR2_Pos (2U)
#define EXTI_PR1_PR2_Msk (0x1U << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PR3_Pos (3U)
#define EXTI_PR1_PR3_Msk (0x1U << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PR4_Pos (4U)
#define EXTI_PR1_PR4_Msk (0x1U << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PR5_Pos (5U)
#define EXTI_PR1_PR5_Msk (0x1U << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PR6_Pos (6U)
#define EXTI_PR1_PR6_Msk (0x1U << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PR7_Pos (7U)
#define EXTI_PR1_PR7_Msk (0x1U << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PR8_Pos (8U)
#define EXTI_PR1_PR8_Msk (0x1U << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PR9_Pos (9U)
#define EXTI_PR1_PR9_Msk (0x1U << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PR10_Pos (10U)
#define EXTI_PR1_PR10_Msk (0x1U << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PR11_Pos (11U)
#define EXTI_PR1_PR11_Msk (0x1U << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PR12_Pos (12U)
#define EXTI_PR1_PR12_Msk (0x1U << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PR13_Pos (13U)
#define EXTI_PR1_PR13_Msk (0x1U << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PR14_Pos (14U)
#define EXTI_PR1_PR14_Msk (0x1U << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PR15_Pos (15U)
#define EXTI_PR1_PR15_Msk (0x1U << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PR16_Pos (16U)
#define EXTI_PR1_PR16_Msk (0x1U << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PR17_Pos (17U)
#define EXTI_PR1_PR17_Msk (0x1U << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PR18_Pos (18U)
#define EXTI_PR1_PR18_Msk (0x1U << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR1_PR19_Pos (19U)
#define EXTI_PR1_PR19_Msk (0x1U << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PR20_Pos (20U)
#define EXTI_PR1_PR20_Msk (0x1U << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PR21_Pos (21U)
#define EXTI_PR1_PR21_Msk (0x1U << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
/******************* Bit definition for EXTI_PR2 register ********************/
#define EXTI_PR2_PR49_Pos (17U)
#define EXTI_PR2_PR49_Msk (0x1U << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
#define EXTI_PR2_PR51_Pos (19U)
#define EXTI_PR2_PR51_Msk (0x1U << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
/******************* Bit definition for EXTI_PR3 register ********************/
#define EXTI_PR3_PR82_Pos (18U)
#define EXTI_PR3_PR82_Msk (0x1U << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
#define EXTI_PR3_PR84_Pos (20U)
#define EXTI_PR3_PR84_Msk (0x1U << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
#define EXTI_PR3_PR85_Pos (21U)
#define EXTI_PR3_PR85_Msk (0x1U << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
#define EXTI_PR3_PR86_Pos (22U)
#define EXTI_PR3_PR86_Msk (0x1U << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/*
* @brief FLASH Total Sectors Number
*/
#define FLASH_SECTOR_TOTAL 16
/******************* Bits definition for FLASH_ACR register **********************/
#define FLASH_ACR_LATENCY 0x00000007U
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_WRHIGHFREQ 0x00000030U
#define FLASH_ACR_WRHIGHFREQ_0 0x00000000U
#define FLASH_ACR_WRHIGHFREQ_1 0x00000010U
#define FLASH_ACR_WRHIGHFREQ_2 0x00000020U
#define FLASH_ACR_WRHIGHFREQ_3 0x00000030U
/******************* Bits definition for FLASH_CR register ***********************/
#define FLASH_CR_LOCK 0x00000001U
#define FLASH_CR_PG 0x00000002U
#define FLASH_CR_SER 0x00000004U
#define FLASH_CR_BER 0x00000008U
#define FLASH_CR_PSIZE 0x00000030U
#define FLASH_CR_PSIZE_0 0x00000010U
#define FLASH_CR_PSIZE_1 0x00000020U
#define FLASH_CR_FW 0x00000040U
#define FLASH_CR_START 0x00000080U
#define FLASH_CR_SNB 0x00000700U
#define FLASH_CR_SNB_0 0x00000000U
#define FLASH_CR_SNB_1 0x00000100U
#define FLASH_CR_SNB_2 0x00000200U
#define FLASH_CR_SNB_3 0x00000300U
#define FLASH_CR_SNB_4 0x00000400U
#define FLASH_CR_SNB_5 0x00000500U
#define FLASH_CR_SNB_6 0x00000600U
#define FLASH_CR_SNB_7 0x00000700U
#define FLASH_CR_CRC_EN 0x00008000U
#define FLASH_CR_EOPIE 0x00010000U
#define FLASH_CR_WRPERRIE 0x00020000U
#define FLASH_CR_PGSERRIE 0x00040000U
#define FLASH_CR_STRBERRIE 0x00080000U
#define FLASH_CR_INCERRIE 0x00200000U
#define FLASH_CR_OPERRIE 0x00400000U
#define FLASH_CR_RDPERRIE 0x00800000U
#define FLASH_CR_RDSERRIE 0x01000000U
#define FLASH_CR_SNECCERRIE 0x02000000U
#define FLASH_CR_DBECCERRIE 0x04000000U
#define FLASH_CR_CRCENDIE 0x08000000U
/******************* Bits definition for FLASH_SR register ***********************/
#define FLASH_SR_BSY 0x00000001U
#define FLASH_SR_WBNE 0x00000002U
#define FLASH_SR_QW 0x00000004U
#define FLASH_SR_CRC_BUSY 0x00000008U
#define FLASH_SR_EOP 0x00010000U
#define FLASH_SR_WRPERR 0x00020000U
#define FLASH_SR_PGSERR 0x00040000U
#define FLASH_SR_STRBERR 0x00080000U
#define FLASH_SR_INCERR 0x00200000U
#define FLASH_SR_OPERR 0x00400000U
#define FLASH_SR_RDPERR 0x00800000U
#define FLASH_SR_RDSERR 0x01000000U
#define FLASH_SR_SNECCERR 0x02000000U
#define FLASH_SR_DBECCERR 0x04000000U
#define FLASH_SR_CRCEND 0x08000000U
/******************* Bits definition for FLASH_CCR register *******************/
#define FLASH_CCR_CLR_EOP 0x00010000U
#define FLASH_CCR_CLR_WRPERR 0x00020000U
#define FLASH_CCR_CLR_PGSERR 0x00040000U
#define FLASH_CCR_CLR_STRBERR 0x00080000U
#define FLASH_CCR_CLR_INCERR 0x00200000U
#define FLASH_CCR_CLR_OPERR 0x00400000U
#define FLASH_CCR_CLR_RDPERR 0x00800000U
#define FLASH_CCR_CLR_RDSERR 0x01000000U
#define FLASH_CCR_CLR_SNECCERR 0x02000000U
#define FLASH_CCR_CLR_DBECCERR 0x04000000U
#define FLASH_CCR_CLR_CRCEND 0x08000000U
/******************* Bits definition for FLASH_OPTCR register *******************/
#define FLASH_OPTCR_OPTLOCK 0x00000001U
#define FLASH_OPTCR_OPTSTART 0x00000002U
#define FLASH_OPTCR_MER 0x00000008U
#define FLASH_OPTCR_OPTCHANGEERRIE 0x40000000U
#define FLASH_OPTCR_SWAP_BANK 0x80000000U
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY 0x00000001U
#define FLASH_OPTSR_BOR_LEV 0x0000000CU
#define FLASH_OPTSR_BOR_LEV_0 0x00000004U
#define FLASH_OPTSR_BOR_LEV_1 0x00000008U
#define FLASH_OPTSR_IWDG1_SW 0x00000010U
#define FLASH_OPTSR_NRST_STOP_D1 0x00000040U
#define FLASH_OPTSR_NRST_STBY_D1 0x00000080U
#define FLASH_OPTSR_RDP 0x0000FF00U
#define FLASH_OPTCR_RDP_0 0x00000100U
#define FLASH_OPTCR_RDP_1 0x00000200U
#define FLASH_OPTCR_RDP_2 0x00000400U
#define FLASH_OPTCR_RDP_3 0x00000800U
#define FLASH_OPTCR_RDP_4 0x00001000U
#define FLASH_OPTCR_RDP_5 0x00002000U
#define FLASH_OPTCR_RDP_6 0x00004000U
#define FLASH_OPTCR_RDP_7 0x00008000U
#define FLASH_OPTSR_FZ_IWDG_STOP 0x00020000U
#define FLASH_OPTSR_FZ_IWDG_SDBY 0x00040000U
#define FLASH_OPTSR_ST_RAM_SIZE 0x00180000U
#define FLASH_OPTSR_ST_RAM_SIZE_0 0x00080000U
#define FLASH_OPTSR_ST_RAM_SIZE_1 0x00100000U
#define FLASH_OPTSR_SECURITY 0x00200000U
#define FLASH_OPTSR_RSS1 0x04000000U
#define FLASH_OPTSR_RSS2 0x08000000U
#define FLASH_OPTSR_PERSO_OK 0x10000000U
#define FLASH_OPTSR_IO_HSLV 0x20000000U
#define FLASH_OPTSR_OPTCHANGEERR 0x40000000U
#define FLASH_OPTSR_SWAP_BANK_OPT 0x80000000U
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR 0x40000000U
/******************* Bits definition for FLASH_PRAR register *********************/
#define FLASH_PRAR_PROT_AREA_START 0x00000FFFU
#define FLASH_PRAR_PROT_AREA_END 0x0FFF0000U
#define FLASH_PRAR_DMEP 0x80000000U
/******************* Bits definition for FLASH_SCAR register *********************/
#define FLASH_SCAR_SEC_AREA_START 0x00000FFFU
#define FLASH_SCAR_SEC_AREA_END 0x0FFF0000U
#define FLASH_SCAR_DMES 0x80000000U
/******************* Bits definition for FLASH_WPSN register *********************/
#define FLASH_WPSN_WRPSN 0x000000FFU
/******************* Bits definition for FLASH_BOOT_CUR register ****************/
#define FLASH_BOOT_ADD0 0x0000FFFFU
#define FLASH_BOOT_ADD1 0xFFFF0000U
/******************* Bits definition for FLASH_CRCCR register ********************/
#define FLASH_CRCCR_CRC_SECT 0x00000007U
#define FLASH_CRCCR_ALL_BANK 0x00000080U
#define FLASH_CRCCR_CRC_BY_SECT 0x00000100U
#define FLASH_CRCCR_ADD_SECT 0x00000200U
#define FLASH_CRCCR_CLEAN_SECT 0x00000400U
#define FLASH_CRCCR_START_CRC 0x00010000U
#define FLASH_CRCCR_CLEAN_CRC 0x00020000U
#define FLASH_CRCCR_CRC_BURST 0x00300000U
#define FLASH_CRCCR_CRC_BURST_0 0x00000000U
#define FLASH_CRCCR_CRC_BURST_1 0x00100000U
#define FLASH_CRCCR_CRC_BURST_2 0x00200000U
#define FLASH_CRCCR_CRC_BURST_3 0x00300000U
/******************* Bits definition for FLASH_CRCSADD register ****************/
#define FLASH_CRCSADD_CRC_START_ADDR 0xFFFFFFFFU
/******************* Bits definition for FLASH_CRCEADD register ****************/
#define FLASH_CRCEADD_CRC_END_ADDR 0xFFFFFFFFU
/******************* Bits definition for FLASH_CRCDATA register ***************/
#define FLASH_CRCDATA_CRC_DATA 0xFFFFFFFFU
/******************* Bits definition for FLASH_ECC_FA register *******************/
#define FLASH_ECC_FA_FAIL_ECC_ADDR 0x00007FFFU
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_MBKEN_Pos (0U)
#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR1_MUXEN_Pos (1U)
#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR1_MTYP_Pos (2U)
#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR1_MWID_Pos (4U)
#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR1_FACCEN_Pos (6U)
#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR1_BURSTEN_Pos (8U)
#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR1_WAITPOL_Pos (9U)
#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR1_WAITCFG_Pos (11U)
#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR1_WREN_Pos (12U)
#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
#define FMC_BCR1_WAITEN_Pos (13U)
#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR1_EXTMOD_Pos (14U)
#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR1_ASYNCWAIT_Pos (15U)
#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR1_CPSIZE_Pos (16U)
#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR1_CBURSTRW_Pos (19U)
#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
#define FMC_BCR1_BMAP_Pos (24U)
#define FMC_BCR1_BMAP_Msk (0x3U << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
#define FMC_BCR1_BMAP_0 (0x1U << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
#define FMC_BCR1_BMAP_1 (0x2U << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
#define FMC_BCR1_FMCEN_Pos (31U)
#define FMC_BCR1_FMCEN_Msk (0x1U << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
/****************** Bit definition for FMC_BCR2 register *******************/
#define FMC_BCR2_MBKEN_Pos (0U)
#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR2_MUXEN_Pos (1U)
#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR2_MTYP_Pos (2U)
#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR2_MWID_Pos (4U)
#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR2_FACCEN_Pos (6U)
#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR2_BURSTEN_Pos (8U)
#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR2_WAITPOL_Pos (9U)
#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR2_WAITCFG_Pos (11U)
#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR2_WREN_Pos (12U)
#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
#define FMC_BCR2_WAITEN_Pos (13U)
#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR2_EXTMOD_Pos (14U)
#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR2_ASYNCWAIT_Pos (15U)
#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR2_CPSIZE_Pos (16U)
#define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR2_CBURSTRW_Pos (19U)
#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
/****************** Bit definition for FMC_BCR3 register *******************/
#define FMC_BCR3_MBKEN_Pos (0U)
#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR3_MUXEN_Pos (1U)
#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR3_MTYP_Pos (2U)
#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR3_MWID_Pos (4U)
#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR3_FACCEN_Pos (6U)
#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR3_BURSTEN_Pos (8U)
#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR3_WAITPOL_Pos (9U)
#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR3_WAITCFG_Pos (11U)
#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR3_WREN_Pos (12U)
#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
#define FMC_BCR3_WAITEN_Pos (13U)
#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR3_EXTMOD_Pos (14U)
#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR3_ASYNCWAIT_Pos (15U)
#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR3_CPSIZE_Pos (16U)
#define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR3_CBURSTRW_Pos (19U)
#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
/****************** Bit definition for FMC_BCR4 register *******************/
#define FMC_BCR4_MBKEN_Pos (0U)
#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR4_MUXEN_Pos (1U)
#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR4_MTYP_Pos (2U)
#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR4_MWID_Pos (4U)
#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR4_FACCEN_Pos (6U)
#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR4_BURSTEN_Pos (8U)
#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR4_WAITPOL_Pos (9U)
#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR4_WAITCFG_Pos (11U)
#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR4_WREN_Pos (12U)
#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
#define FMC_BCR4_WAITEN_Pos (13U)
#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR4_EXTMOD_Pos (14U)
#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR4_ASYNCWAIT_Pos (15U)
#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR4_CPSIZE_Pos (16U)
#define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR4_CBURSTRW_Pos (19U)
#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
/****************** Bit definition for FMC_BTR1 register ******************/
#define FMC_BTR1_ADDSET_Pos (0U)
#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR1_ADDHLD_Pos (4U)
#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR1_DATAST_Pos (8U)
#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR1_BUSTURN_Pos (16U)
#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR1_CLKDIV_Pos (20U)
#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR1_DATLAT_Pos (24U)
#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR1_ACCMOD_Pos (28U)
#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BTR2 register *******************/
#define FMC_BTR2_ADDSET_Pos (0U)
#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR2_ADDHLD_Pos (4U)
#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR2_DATAST_Pos (8U)
#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR2_BUSTURN_Pos (16U)
#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR2_CLKDIV_Pos (20U)
#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR2_DATLAT_Pos (24U)
#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR2_ACCMOD_Pos (28U)
#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
/******************* Bit definition for FMC_BTR3 register *******************/
#define FMC_BTR3_ADDSET_Pos (0U)
#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR3_ADDHLD_Pos (4U)
#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR3_DATAST_Pos (8U)
#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR3_BUSTURN_Pos (16U)
#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR3_CLKDIV_Pos (20U)
#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR3_DATLAT_Pos (24U)
#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR3_ACCMOD_Pos (28U)
#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BTR4 register *******************/
#define FMC_BTR4_ADDSET_Pos (0U)
#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR4_ADDHLD_Pos (4U)
#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR4_DATAST_Pos (8U)
#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR4_BUSTURN_Pos (16U)
#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR4_CLKDIV_Pos (20U)
#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR4_DATLAT_Pos (24U)
#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR4_ACCMOD_Pos (28U)
#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BWTR1 register ******************/
#define FMC_BWTR1_ADDSET_Pos (0U)
#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR1_ADDHLD_Pos (4U)
#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR1_DATAST_Pos (8U)
#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR1_BUSTURN_Pos (16U)
#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTR1_ACCMOD_Pos (28U)
#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BWTR2 register ******************/
#define FMC_BWTR2_ADDSET_Pos (0U)
#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR2_ADDHLD_Pos (4U)
#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR2_DATAST_Pos (8U)
#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR2_BUSTURN_Pos (16U)
#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTR2_ACCMOD_Pos (28U)
#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BWTR3 register ******************/
#define FMC_BWTR3_ADDSET_Pos (0U)
#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR3_ADDHLD_Pos (4U)
#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR3_DATAST_Pos (8U)
#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR3_BUSTURN_Pos (16U)
#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTR3_ACCMOD_Pos (28U)
#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_BWTR4 register ******************/
#define FMC_BWTR4_ADDSET_Pos (0U)
#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR4_ADDHLD_Pos (4U)
#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR4_DATAST_Pos (8U)
#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR4_BUSTURN_Pos (16U)
#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTR4_ACCMOD_Pos (28U)
#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
/****************** Bit definition for FMC_PCR register *******************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos (17U)
#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
/******************* Bit definition for FMC_SR register *******************/
#define FMC_SR_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FMC_SR_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FMC_SR_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FMC_SR_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FMC_SR_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET3_Pos (0U)
#define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
#define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT3_Pos (8U)
#define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
#define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD3_Pos (16U)
#define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
#define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ3_Pos (24U)
#define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
#define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register ******************/
#define FMC_PATT_ATTSET3_Pos (0U)
#define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
#define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT3_Pos (8U)
#define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
#define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD3_Pos (16U)
#define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
#define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ3_Pos (24U)
#define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
#define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_ECCR3 register ******************/
#define FMC_ECCR3_ECC3_Pos (0U)
#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
/****************** Bit definition for FMC_SDCR1 register ******************/
#define FMC_SDCR1_NC_Pos (0U)
#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
#define FMC_SDCR1_NR_Pos (2U)
#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
#define FMC_SDCR1_MWID_Pos (4U)
#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
#define FMC_SDCR1_NB_Pos (6U)
#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
#define FMC_SDCR1_CAS_Pos (7U)
#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
#define FMC_SDCR1_WP_Pos (9U)
#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
#define FMC_SDCR1_SDCLK_Pos (10U)
#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
#define FMC_SDCR1_RBURST_Pos (12U)
#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
#define FMC_SDCR1_RPIPE_Pos (13U)
#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
/****************** Bit definition for FMC_SDCR2 register ******************/
#define FMC_SDCR2_NC_Pos (0U)
#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
#define FMC_SDCR2_NR_Pos (2U)
#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
#define FMC_SDCR2_MWID_Pos (4U)
#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
#define FMC_SDCR2_NB_Pos (6U)
#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
#define FMC_SDCR2_CAS_Pos (7U)
#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
#define FMC_SDCR2_WP_Pos (9U)
#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
#define FMC_SDCR2_SDCLK_Pos (10U)
#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
/****************** Bit definition for FMC_SDTR1 register ******************/
#define FMC_SDTR1_TMRD_Pos (0U)
#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
#define FMC_SDTR1_TXSR_Pos (4U)
#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
#define FMC_SDTR1_TRAS_Pos (8U)
#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
#define FMC_SDTR1_TRC_Pos (12U)
#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
#define FMC_SDTR1_TWR_Pos (16U)
#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
#define FMC_SDTR1_TRP_Pos (20U)
#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
#define FMC_SDTR1_TRCD_Pos (24U)
#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
/****************** Bit definition for FMC_SDTR2 register ******************/
#define FMC_SDTR2_TMRD_Pos (0U)
#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
#define FMC_SDTR2_TXSR_Pos (4U)
#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
#define FMC_SDTR2_TRAS_Pos (8U)
#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
#define FMC_SDTR2_TRC_Pos (12U)
#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
#define FMC_SDTR2_TWR_Pos (16U)
#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
#define FMC_SDTR2_TRP_Pos (20U)
#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
#define FMC_SDTR2_TRCD_Pos (24U)
#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
/****************** Bit definition for FMC_SDCMR register ******************/
#define FMC_SDCMR_MODE_Pos (0U)
#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
#define FMC_SDCMR_MODE_2 (0x3U << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
#define FMC_SDCMR_CTB2_Pos (3U)
#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
#define FMC_SDCMR_CTB1_Pos (4U)
#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
#define FMC_SDCMR_NRFS_Pos (5U)
#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
#define FMC_SDCMR_MRD_Pos (9U)
#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
/****************** Bit definition for FMC_SDRTR register ******************/
#define FMC_SDRTR_CRE_Pos (0U)
#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
#define FMC_SDRTR_COUNT_Pos (1U)
#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
#define FMC_SDSR_MODES1_Pos (1U)
#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
#define FMC_SDSR_MODES2_Pos (3U)
#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
/******************************************************************************/
/* */
/* General Purpose I/O */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0_Pos (0U)
#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODER1_Pos (2U)
#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODER2_Pos (4U)
#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODER3_Pos (6U)
#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODER4_Pos (8U)
#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODER5_Pos (10U)
#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODER6_Pos (12U)
#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODER7_Pos (14U)
#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODER8_Pos (16U)
#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODER9_Pos (18U)
#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODER10_Pos (20U)
#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODER11_Pos (22U)
#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODER12_Pos (24U)
#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODER13_Pos (26U)
#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODER14_Pos (28U)
#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODER15_Pos (30U)
#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPDR1_Pos (2U)
#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPDR2_Pos (4U)
#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPDR3_Pos (6U)
#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPDR4_Pos (8U)
#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPDR5_Pos (10U)
#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPDR6_Pos (12U)
#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPDR7_Pos (14U)
#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPDR8_Pos (16U)
#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPDR9_Pos (18U)
#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPDR10_Pos (20U)
#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPDR11_Pos (22U)
#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPDR12_Pos (24U)
#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPDR13_Pos (26U)
#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPDR14_Pos (28U)
#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPDR15_Pos (30U)
#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
/****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
#define GPIO_AFRH_AFRH1_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
#define GPIO_AFRH_AFRH2_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
#define GPIO_AFRH_AFRH3_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
#define GPIO_AFRH_AFRH4_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
#define GPIO_AFRH_AFRH5_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
#define GPIO_AFRH_AFRH6_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
#define GPIO_AFRH_AFRH7_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
/******************************************************************************/
/* */
/* HSEM HW Semaphore */
/* */
/******************************************************************************/
/******************** Bit definition for HSEM_R register ********************/
#define HSEM_R_PROCID_Pos (0U)
#define HSEM_R_PROCID_Msk (0xFFU << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
#define HSEM_R_MASTERID_Pos (8U)
#define HSEM_R_MASTERID_Msk (0xFFU << HSEM_R_MASTERID_Pos) /*!< 0x0000FF00 */
#define HSEM_R_MASTERID HSEM_R_MASTERID_Msk /*!<Semaphore MasterID. */
#define HSEM_R_LOCK_Pos (31U)
#define HSEM_R_LOCK_Msk (0x1U << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
/******************** Bit definition for HSEM_RLR register ******************/
#define HSEM_RLR_PROCID_Pos (0U)
#define HSEM_RLR_PROCID_Msk (0xFFU << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
#define HSEM_RLR_MASTERID_Pos (8U)
#define HSEM_RLR_MASTERID_Msk (0xFFU << HSEM_RLR_MASTERID_Pos) /*!< 0x0000FF00 */
#define HSEM_RLR_MASTERID HSEM_RLR_MASTERID_Msk /*!<Semaphore MasterID. */
#define HSEM_RLR_LOCK_Pos (31U)
#define HSEM_RLR_LOCK_Msk (0x1U << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
/******************** Bit definition for HSEM_IER register *****************/
#define HSEM_IER_ISEM0_Pos (0U)
#define HSEM_IER_ISEM0_Msk (0x1U << HSEM_IER_ISEM0_Pos) /*!< 0x00000001 */
#define HSEM_IER_ISEM0 HSEM_IER_ISEM0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
#define HSEM_IER_ISEM1_Pos (1U)
#define HSEM_IER_ISEM1_Msk (0x1U << HSEM_IER_ISEM1_Pos) /*!< 0x00000002 */
#define HSEM_IER_ISEM1 HSEM_IER_ISEM1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
#define HSEM_IER_ISEM2_Pos (2U)
#define HSEM_IER_ISEM2_Msk (0x1U << HSEM_IER_ISEM2_Pos) /*!< 0x00000004 */
#define HSEM_IER_ISEM2 HSEM_IER_ISEM2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
#define HSEM_IER_ISEM3_Pos (3U)
#define HSEM_IER_ISEM3_Msk (0x1U << HSEM_IER_ISEM3_Pos) /*!< 0x00000008 */
#define HSEM_IER_ISEM3 HSEM_IER_ISEM3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
#define HSEM_IER_ISEM4_Pos (4U)
#define HSEM_IER_ISEM4_Msk (0x1U << HSEM_IER_ISEM4_Pos) /*!< 0x00000010 */
#define HSEM_IER_ISEM4 HSEM_IER_ISEM4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
#define HSEM_IER_ISEM5_Pos (5U)
#define HSEM_IER_ISEM5_Msk (0x1U << HSEM_IER_ISEM5_Pos) /*!< 0x00000020 */
#define HSEM_IER_ISEM5 HSEM_IER_ISEM5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
#define HSEM_IER_ISEM6_Pos (6U)
#define HSEM_IER_ISEM6_Msk (0x1U << HSEM_IER_ISEM6_Pos) /*!< 0x00000040 */
#define HSEM_IER_ISEM6 HSEM_IER_ISEM6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
#define HSEM_IER_ISEM7_Pos (7U)
#define HSEM_IER_ISEM7_Msk (0x1U << HSEM_IER_ISEM7_Pos) /*!< 0x00000080 */
#define HSEM_IER_ISEM7 HSEM_IER_ISEM7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
#define HSEM_IER_ISEM8_Pos (8U)
#define HSEM_IER_ISEM8_Msk (0x1U << HSEM_IER_ISEM8_Pos) /*!< 0x00000100 */
#define HSEM_IER_ISEM8 HSEM_IER_ISEM8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
#define HSEM_IER_ISEM9_Pos (9U)
#define HSEM_IER_ISEM9_Msk (0x1U << HSEM_IER_ISEM9_Pos) /*!< 0x00000200 */
#define HSEM_IER_ISEM9 HSEM_IER_ISEM9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
#define HSEM_IER_ISEM10_Pos (10U)
#define HSEM_IER_ISEM10_Msk (0x1U << HSEM_IER_ISEM10_Pos) /*!< 0x00000400 */
#define HSEM_IER_ISEM10 HSEM_IER_ISEM10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
#define HSEM_IER_ISEM11_Pos (11U)
#define HSEM_IER_ISEM11_Msk (0x1U << HSEM_IER_ISEM11_Pos) /*!< 0x00000800 */
#define HSEM_IER_ISEM11 HSEM_IER_ISEM11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
#define HSEM_IER_ISEM12_Pos (12U)
#define HSEM_IER_ISEM12_Msk (0x1U << HSEM_IER_ISEM12_Pos) /*!< 0x00001000 */
#define HSEM_IER_ISEM12 HSEM_IER_ISEM12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
#define HSEM_IER_ISEM13_Pos (13U)
#define HSEM_IER_ISEM13_Msk (0x1U << HSEM_IER_ISEM13_Pos) /*!< 0x00002000 */
#define HSEM_IER_ISEM13 HSEM_IER_ISEM13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
#define HSEM_IER_ISEM14_Pos (14U)
#define HSEM_IER_ISEM14_Msk (0x1U << HSEM_IER_ISEM14_Pos) /*!< 0x00004000 */
#define HSEM_IER_ISEM14 HSEM_IER_ISEM14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
#define HSEM_IER_ISEM15_Pos (15U)
#define HSEM_IER_ISEM15_Msk (0x1U << HSEM_IER_ISEM15_Pos) /*!< 0x00008000 */
#define HSEM_IER_ISEM15 HSEM_IER_ISEM15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
#define HSEM_IER_ISEM16_Pos (16U)
#define HSEM_IER_ISEM16_Msk (0x1U << HSEM_IER_ISEM16_Pos) /*!< 0x00010000 */
#define HSEM_IER_ISEM16 HSEM_IER_ISEM16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
#define HSEM_IER_ISEM17_Pos (17U)
#define HSEM_IER_ISEM17_Msk (0x1U << HSEM_IER_ISEM17_Pos) /*!< 0x00020000 */
#define HSEM_IER_ISEM17 HSEM_IER_ISEM17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
#define HSEM_IER_ISEM18_Pos (18U)
#define HSEM_IER_ISEM18_Msk (0x1U << HSEM_IER_ISEM18_Pos) /*!< 0x00040000 */
#define HSEM_IER_ISEM18 HSEM_IER_ISEM18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
#define HSEM_IER_ISEM19_Pos (19U)
#define HSEM_IER_ISEM19_Msk (0x1U << HSEM_IER_ISEM19_Pos) /*!< 0x00080000 */
#define HSEM_IER_ISEM19 HSEM_IER_ISEM19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
#define HSEM_IER_ISEM20_Pos (20U)
#define HSEM_IER_ISEM20_Msk (0x1U << HSEM_IER_ISEM20_Pos) /*!< 0x00100000 */
#define HSEM_IER_ISEM20 HSEM_IER_ISEM20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
#define HSEM_IER_ISEM21_Pos (21U)
#define HSEM_IER_ISEM21_Msk (0x1U << HSEM_IER_ISEM21_Pos) /*!< 0x00200000 */
#define HSEM_IER_ISEM21 HSEM_IER_ISEM21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
#define HSEM_IER_ISEM22_Pos (22U)
#define HSEM_IER_ISEM22_Msk (0x1U << HSEM_IER_ISEM22_Pos) /*!< 0x00400000 */
#define HSEM_IER_ISEM22 HSEM_IER_ISEM22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
#define HSEM_IER_ISEM23_Pos (23U)
#define HSEM_IER_ISEM23_Msk (0x1U << HSEM_IER_ISEM23_Pos) /*!< 0x00800000 */
#define HSEM_IER_ISEM23 HSEM_IER_ISEM23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
#define HSEM_IER_ISEM24_Pos (24U)
#define HSEM_IER_ISEM24_Msk (0x1U << HSEM_IER_ISEM24_Pos) /*!< 0x01000000 */
#define HSEM_IER_ISEM24 HSEM_IER_ISEM24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
#define HSEM_IER_ISEM25_Pos (25U)
#define HSEM_IER_ISEM25_Msk (0x1U << HSEM_IER_ISEM25_Pos) /*!< 0x02000000 */
#define HSEM_IER_ISEM25 HSEM_IER_ISEM25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
#define HSEM_IER_ISEM26_Pos (26U)
#define HSEM_IER_ISEM26_Msk (0x1U << HSEM_IER_ISEM26_Pos) /*!< 0x04000000 */
#define HSEM_IER_ISEM26 HSEM_IER_ISEM26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
#define HSEM_IER_ISEM27_Pos (27U)
#define HSEM_IER_ISEM27_Msk (0x1U << HSEM_IER_ISEM27_Pos) /*!< 0x08000000 */
#define HSEM_IER_ISEM27 HSEM_IER_ISEM27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
#define HSEM_IER_ISEM28_Pos (28U)
#define HSEM_IER_ISEM28_Msk (0x1U << HSEM_IER_ISEM28_Pos) /*!< 0x10000000 */
#define HSEM_IER_ISEM28 HSEM_IER_ISEM28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
#define HSEM_IER_ISEM29_Pos (29U)
#define HSEM_IER_ISEM29_Msk (0x1U << HSEM_IER_ISEM29_Pos) /*!< 0x20000000 */
#define HSEM_IER_ISEM29 HSEM_IER_ISEM29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
#define HSEM_IER_ISEM30_Pos (30U)
#define HSEM_IER_ISEM30_Msk (0x1U << HSEM_IER_ISEM30_Pos) /*!< 0x40000000 */
#define HSEM_IER_ISEM30 HSEM_IER_ISEM30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
#define HSEM_IER_ISEM31_Pos (31U)
#define HSEM_IER_ISEM31_Msk (0x1U << HSEM_IER_ISEM31_Pos) /*!< 0x80000000 */
#define HSEM_IER_ISEM31 HSEM_IER_ISEM31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
/******************** Bit definition for HSEM_ICR register *****************/
#define HSEM_ICR_ISEM0_Pos (0U)
#define HSEM_ICR_ISEM0_Msk (0x1U << HSEM_ICR_ISEM0_Pos) /*!< 0x00000001 */
#define HSEM_ICR_ISEM0 HSEM_ICR_ISEM0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
#define HSEM_ICR_ISEM1_Pos (1U)
#define HSEM_ICR_ISEM1_Msk (0x1U << HSEM_ICR_ISEM1_Pos) /*!< 0x00000002 */
#define HSEM_ICR_ISEM1 HSEM_ICR_ISEM1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
#define HSEM_ICR_ISEM2_Pos (2U)
#define HSEM_ICR_ISEM2_Msk (0x1U << HSEM_ICR_ISEM2_Pos) /*!< 0x00000004 */
#define HSEM_ICR_ISEM2 HSEM_ICR_ISEM2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
#define HSEM_ICR_ISEM3_Pos (3U)
#define HSEM_ICR_ISEM3_Msk (0x1U << HSEM_ICR_ISEM3_Pos) /*!< 0x00000008 */
#define HSEM_ICR_ISEM3 HSEM_ICR_ISEM3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
#define HSEM_ICR_ISEM4_Pos (4U)
#define HSEM_ICR_ISEM4_Msk (0x1U << HSEM_ICR_ISEM4_Pos) /*!< 0x00000010 */
#define HSEM_ICR_ISEM4 HSEM_ICR_ISEM4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
#define HSEM_ICR_ISEM5_Pos (5U)
#define HSEM_ICR_ISEM5_Msk (0x1U << HSEM_ICR_ISEM5_Pos) /*!< 0x00000020 */
#define HSEM_ICR_ISEM5 HSEM_ICR_ISEM5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM6_Pos (6U)
#define HSEM_ICR_ISEM6_Msk (0x1U << HSEM_ICR_ISEM6_Pos) /*!< 0x00000040 */
#define HSEM_ICR_ISEM6 HSEM_ICR_ISEM6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM7_Pos (7U)
#define HSEM_ICR_ISEM7_Msk (0x1U << HSEM_ICR_ISEM7_Pos) /*!< 0x00000080 */
#define HSEM_ICR_ISEM7 HSEM_ICR_ISEM7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM8_Pos (8U)
#define HSEM_ICR_ISEM8_Msk (0x1U << HSEM_ICR_ISEM8_Pos) /*!< 0x00000100 */
#define HSEM_ICR_ISEM8 HSEM_ICR_ISEM8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM9_Pos (9U)
#define HSEM_ICR_ISEM9_Msk (0x1U << HSEM_ICR_ISEM9_Pos) /*!< 0x00000200 */
#define HSEM_ICR_ISEM9 HSEM_ICR_ISEM9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM10_Pos (10U)
#define HSEM_ICR_ISEM10_Msk (0x1U << HSEM_ICR_ISEM10_Pos) /*!< 0x00000400 */
#define HSEM_ICR_ISEM10 HSEM_ICR_ISEM10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM11_Pos (11U)
#define HSEM_ICR_ISEM11_Msk (0x1U << HSEM_ICR_ISEM11_Pos) /*!< 0x00000800 */
#define HSEM_ICR_ISEM11 HSEM_ICR_ISEM11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM12_Pos (12U)
#define HSEM_ICR_ISEM12_Msk (0x1U << HSEM_ICR_ISEM12_Pos) /*!< 0x00001000 */
#define HSEM_ICR_ISEM12 HSEM_ICR_ISEM12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM13_Pos (13U)
#define HSEM_ICR_ISEM13_Msk (0x1U << HSEM_ICR_ISEM13_Pos) /*!< 0x00002000 */
#define HSEM_ICR_ISEM13 HSEM_ICR_ISEM13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM14_Pos (14U)
#define HSEM_ICR_ISEM14_Msk (0x1U << HSEM_ICR_ISEM14_Pos) /*!< 0x00004000 */
#define HSEM_ICR_ISEM14 HSEM_ICR_ISEM14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM15_Pos (15U)
#define HSEM_ICR_ISEM15_Msk (0x1U << HSEM_ICR_ISEM15_Pos) /*!< 0x00008000 */
#define HSEM_ICR_ISEM15 HSEM_ICR_ISEM15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM16_Pos (16U)
#define HSEM_ICR_ISEM16_Msk (0x1U << HSEM_ICR_ISEM16_Pos) /*!< 0x00010000 */
#define HSEM_ICR_ISEM16 HSEM_ICR_ISEM16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM17_Pos (17U)
#define HSEM_ICR_ISEM17_Msk (0x1U << HSEM_ICR_ISEM17_Pos) /*!< 0x00020000 */
#define HSEM_ICR_ISEM17 HSEM_ICR_ISEM17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM18_Pos (18U)
#define HSEM_ICR_ISEM18_Msk (0x1U << HSEM_ICR_ISEM18_Pos) /*!< 0x00040000 */
#define HSEM_ICR_ISEM18 HSEM_ICR_ISEM18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM19_Pos (19U)
#define HSEM_ICR_ISEM19_Msk (0x1U << HSEM_ICR_ISEM19_Pos) /*!< 0x00080000 */
#define HSEM_ICR_ISEM19 HSEM_ICR_ISEM19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM20_Pos (20U)
#define HSEM_ICR_ISEM20_Msk (0x1U << HSEM_ICR_ISEM20_Pos) /*!< 0x00100000 */
#define HSEM_ICR_ISEM20 HSEM_ICR_ISEM20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM21_Pos (21U)
#define HSEM_ICR_ISEM21_Msk (0x1U << HSEM_ICR_ISEM21_Pos) /*!< 0x00200000 */
#define HSEM_ICR_ISEM21 HSEM_ICR_ISEM21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM22_Pos (22U)
#define HSEM_ICR_ISEM22_Msk (0x1U << HSEM_ICR_ISEM22_Pos) /*!< 0x00400000 */
#define HSEM_ICR_ISEM22 HSEM_ICR_ISEM22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM23_Pos (23U)
#define HSEM_ICR_ISEM23_Msk (0x1U << HSEM_ICR_ISEM23_Pos) /*!< 0x00800000 */
#define HSEM_ICR_ISEM23 HSEM_ICR_ISEM23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM24_Pos (24U)
#define HSEM_ICR_ISEM24_Msk (0x1U << HSEM_ICR_ISEM24_Pos) /*!< 0x01000000 */
#define HSEM_ICR_ISEM24 HSEM_ICR_ISEM24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM25_Pos (25U)
#define HSEM_ICR_ISEM25_Msk (0x1U << HSEM_ICR_ISEM25_Pos) /*!< 0x02000000 */
#define HSEM_ICR_ISEM25 HSEM_ICR_ISEM25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM26_Pos (26U)
#define HSEM_ICR_ISEM26_Msk (0x1U << HSEM_ICR_ISEM26_Pos) /*!< 0x04000000 */
#define HSEM_ICR_ISEM26 HSEM_ICR_ISEM26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM27_Pos (27U)
#define HSEM_ICR_ISEM27_Msk (0x1U << HSEM_ICR_ISEM27_Pos) /*!< 0x08000000 */
#define HSEM_ICR_ISEM27 HSEM_ICR_ISEM27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM28_Pos (28U)
#define HSEM_ICR_ISEM28_Msk (0x1U << HSEM_ICR_ISEM28_Pos) /*!< 0x10000000 */
#define HSEM_ICR_ISEM28 HSEM_ICR_ISEM28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM29_Pos (29U)
#define HSEM_ICR_ISEM29_Msk (0x1U << HSEM_ICR_ISEM29_Pos) /*!< 0x20000000 */
#define HSEM_ICR_ISEM29 HSEM_ICR_ISEM29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM30_Pos (30U)
#define HSEM_ICR_ISEM30_Msk (0x1U << HSEM_ICR_ISEM30_Pos) /*!< 0x40000000 */
#define HSEM_ICR_ISEM30 HSEM_ICR_ISEM30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
#define HSEM_ICR_ISEM31_Pos (31U)
#define HSEM_ICR_ISEM31_Msk (0x1U << HSEM_ICR_ISEM31_Pos) /*!< 0x80000000 */
#define HSEM_ICR_ISEM31 HSEM_ICR_ISEM31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
/******************** Bit definition for HSEM_ISR register *****************/
#define HSEM_ISR_ISEM0_Pos (0U)
#define HSEM_ISR_ISEM0_Msk (0x1U << HSEM_ISR_ISEM0_Pos) /*!< 0x00000001 */
#define HSEM_ISR_ISEM0 HSEM_ISR_ISEM0_Msk /*!<semaphore 0 interrupt 0 status bit. */
#define HSEM_ISR_ISEM1_Pos (1U)
#define HSEM_ISR_ISEM1_Msk (0x1U << HSEM_ISR_ISEM1_Pos) /*!< 0x00000002 */
#define HSEM_ISR_ISEM1 HSEM_ISR_ISEM1_Msk /*!<semaphore 1 interrupt 0 status bit. */
#define HSEM_ISR_ISEM2_Pos (2U)
#define HSEM_ISR_ISEM2_Msk (0x1U << HSEM_ISR_ISEM2_Pos) /*!< 0x00000004 */
#define HSEM_ISR_ISEM2 HSEM_ISR_ISEM2_Msk /*!<semaphore 2 interrupt 0 status bit. */
#define HSEM_ISR_ISEM3_Pos (3U)
#define HSEM_ISR_ISEM3_Msk (0x1U << HSEM_ISR_ISEM3_Pos) /*!< 0x00000008 */
#define HSEM_ISR_ISEM3 HSEM_ISR_ISEM3_Msk /*!<semaphore 3 interrupt 0 status bit. */
#define HSEM_ISR_ISEM4_Pos (4U)
#define HSEM_ISR_ISEM4_Msk (0x1U << HSEM_ISR_ISEM4_Pos) /*!< 0x00000010 */
#define HSEM_ISR_ISEM4 HSEM_ISR_ISEM4_Msk /*!<semaphore 4 interrupt 0 status bit. */
#define HSEM_ISR_ISEM5_Pos (5U)
#define HSEM_ISR_ISEM5_Msk (0x1U << HSEM_ISR_ISEM5_Pos) /*!< 0x00000020 */
#define HSEM_ISR_ISEM5 HSEM_ISR_ISEM5_Msk /*!<semaphore 5 interrupt 0 status bit. */
#define HSEM_ISR_ISEM6_Pos (6U)
#define HSEM_ISR_ISEM6_Msk (0x1U << HSEM_ISR_ISEM6_Pos) /*!< 0x00000040 */
#define HSEM_ISR_ISEM6 HSEM_ISR_ISEM6_Msk /*!<semaphore 6 interrupt 0 status bit. */
#define HSEM_ISR_ISEM7_Pos (7U)
#define HSEM_ISR_ISEM7_Msk (0x1U << HSEM_ISR_ISEM7_Pos) /*!< 0x00000080 */
#define HSEM_ISR_ISEM7 HSEM_ISR_ISEM7_Msk /*!<semaphore 7 interrupt 0 status bit. */
#define HSEM_ISR_ISEM8_Pos (8U)
#define HSEM_ISR_ISEM8_Msk (0x1U << HSEM_ISR_ISEM8_Pos) /*!< 0x00000100 */
#define HSEM_ISR_ISEM8 HSEM_ISR_ISEM8_Msk /*!<semaphore 8 interrupt 0 status bit. */
#define HSEM_ISR_ISEM9_Pos (9U)
#define HSEM_ISR_ISEM9_Msk (0x1U << HSEM_ISR_ISEM9_Pos) /*!< 0x00000200 */
#define HSEM_ISR_ISEM9 HSEM_ISR_ISEM9_Msk /*!<semaphore 9 interrupt 0 status bit. */
#define HSEM_ISR_ISEM10_Pos (10U)
#define HSEM_ISR_ISEM10_Msk (0x1U << HSEM_ISR_ISEM10_Pos) /*!< 0x00000400 */
#define HSEM_ISR_ISEM10 HSEM_ISR_ISEM10_Msk /*!<semaphore 10 interrupt 0 status bit. */
#define HSEM_ISR_ISEM11_Pos (11U)
#define HSEM_ISR_ISEM11_Msk (0x1U << HSEM_ISR_ISEM11_Pos) /*!< 0x00000800 */
#define HSEM_ISR_ISEM11 HSEM_ISR_ISEM11_Msk /*!<semaphore 11 interrupt 0 status bit. */
#define HSEM_ISR_ISEM12_Pos (12U)
#define HSEM_ISR_ISEM12_Msk (0x1U << HSEM_ISR_ISEM12_Pos) /*!< 0x00001000 */
#define HSEM_ISR_ISEM12 HSEM_ISR_ISEM12_Msk /*!<semaphore 12 interrupt 0 status bit. */
#define HSEM_ISR_ISEM13_Pos (13U)
#define HSEM_ISR_ISEM13_Msk (0x1U << HSEM_ISR_ISEM13_Pos) /*!< 0x00002000 */
#define HSEM_ISR_ISEM13 HSEM_ISR_ISEM13_Msk /*!<semaphore 13 interrupt 0 status bit. */
#define HSEM_ISR_ISEM14_Pos (14U)
#define HSEM_ISR_ISEM14_Msk (0x1U << HSEM_ISR_ISEM14_Pos) /*!< 0x00004000 */
#define HSEM_ISR_ISEM14 HSEM_ISR_ISEM14_Msk /*!<semaphore 14 interrupt 0 status bit. */
#define HSEM_ISR_ISEM15_Pos (15U)
#define HSEM_ISR_ISEM15_Msk (0x1U << HSEM_ISR_ISEM15_Pos) /*!< 0x00008000 */
#define HSEM_ISR_ISEM15 HSEM_ISR_ISEM15_Msk /*!<semaphore 15 interrupt 0 status bit. */
#define HSEM_ISR_ISEM16_Pos (16U)
#define HSEM_ISR_ISEM16_Msk (0x1U << HSEM_ISR_ISEM16_Pos) /*!< 0x00010000 */
#define HSEM_ISR_ISEM16 HSEM_ISR_ISEM16_Msk /*!<semaphore 16 interrupt 0 status bit. */
#define HSEM_ISR_ISEM17_Pos (17U)
#define HSEM_ISR_ISEM17_Msk (0x1U << HSEM_ISR_ISEM17_Pos) /*!< 0x00020000 */
#define HSEM_ISR_ISEM17 HSEM_ISR_ISEM17_Msk /*!<semaphore 17 interrupt 0 status bit. */
#define HSEM_ISR_ISEM18_Pos (18U)
#define HSEM_ISR_ISEM18_Msk (0x1U << HSEM_ISR_ISEM18_Pos) /*!< 0x00040000 */
#define HSEM_ISR_ISEM18 HSEM_ISR_ISEM18_Msk /*!<semaphore 18 interrupt 0 status bit. */
#define HSEM_ISR_ISEM19_Pos (19U)
#define HSEM_ISR_ISEM19_Msk (0x1U << HSEM_ISR_ISEM19_Pos) /*!< 0x00080000 */
#define HSEM_ISR_ISEM19 HSEM_ISR_ISEM19_Msk /*!<semaphore 19 interrupt 0 status bit. */
#define HSEM_ISR_ISEM20_Pos (20U)
#define HSEM_ISR_ISEM20_Msk (0x1U << HSEM_ISR_ISEM20_Pos) /*!< 0x00100000 */
#define HSEM_ISR_ISEM20 HSEM_ISR_ISEM20_Msk /*!<semaphore 20 interrupt 0 status bit. */
#define HSEM_ISR_ISEM21_Pos (21U)
#define HSEM_ISR_ISEM21_Msk (0x1U << HSEM_ISR_ISEM21_Pos) /*!< 0x00200000 */
#define HSEM_ISR_ISEM21 HSEM_ISR_ISEM21_Msk /*!<semaphore 21 interrupt 0 status bit. */
#define HSEM_ISR_ISEM22_Pos (22U)
#define HSEM_ISR_ISEM22_Msk (0x1U << HSEM_ISR_ISEM22_Pos) /*!< 0x00400000 */
#define HSEM_ISR_ISEM22 HSEM_ISR_ISEM22_Msk /*!<semaphore 22 interrupt 0 status bit. */
#define HSEM_ISR_ISEM23_Pos (23U)
#define HSEM_ISR_ISEM23_Msk (0x1U << HSEM_ISR_ISEM23_Pos) /*!< 0x00800000 */
#define HSEM_ISR_ISEM23 HSEM_ISR_ISEM23_Msk /*!<semaphore 23 interrupt 0 status bit. */
#define HSEM_ISR_ISEM24_Pos (24U)
#define HSEM_ISR_ISEM24_Msk (0x1U << HSEM_ISR_ISEM24_Pos) /*!< 0x01000000 */
#define HSEM_ISR_ISEM24 HSEM_ISR_ISEM24_Msk /*!<semaphore 24 interrupt 0 status bit. */
#define HSEM_ISR_ISEM25_Pos (25U)
#define HSEM_ISR_ISEM25_Msk (0x1U << HSEM_ISR_ISEM25_Pos) /*!< 0x02000000 */
#define HSEM_ISR_ISEM25 HSEM_ISR_ISEM25_Msk /*!<semaphore 25 interrupt 0 status bit. */
#define HSEM_ISR_ISEM26_Pos (26U)
#define HSEM_ISR_ISEM26_Msk (0x1U << HSEM_ISR_ISEM26_Pos) /*!< 0x04000000 */
#define HSEM_ISR_ISEM26 HSEM_ISR_ISEM26_Msk /*!<semaphore 26 interrupt 0 status bit. */
#define HSEM_ISR_ISEM27_Pos (27U)
#define HSEM_ISR_ISEM27_Msk (0x1U << HSEM_ISR_ISEM27_Pos) /*!< 0x08000000 */
#define HSEM_ISR_ISEM27 HSEM_ISR_ISEM27_Msk /*!<semaphore 27 interrupt 0 status bit. */
#define HSEM_ISR_ISEM28_Pos (28U)
#define HSEM_ISR_ISEM28_Msk (0x1U << HSEM_ISR_ISEM28_Pos) /*!< 0x10000000 */
#define HSEM_ISR_ISEM28 HSEM_ISR_ISEM28_Msk /*!<semaphore 28 interrupt 0 status bit. */
#define HSEM_ISR_ISEM29_Pos (29U)
#define HSEM_ISR_ISEM29_Msk (0x1U << HSEM_ISR_ISEM29_Pos) /*!< 0x20000000 */
#define HSEM_ISR_ISEM29 HSEM_ISR_ISEM29_Msk /*!<semaphore 29 interrupt 0 status bit. */
#define HSEM_ISR_ISEM30_Pos (30U)
#define HSEM_ISR_ISEM30_Msk (0x1U << HSEM_ISR_ISEM30_Pos) /*!< 0x40000000 */
#define HSEM_ISR_ISEM30 HSEM_ISR_ISEM30_Msk /*!<semaphore 30 interrupt 0 status bit. */
#define HSEM_ISR_ISEM31_Pos (31U)
#define HSEM_ISR_ISEM31_Msk (0x1U << HSEM_ISR_ISEM31_Pos) /*!< 0x80000000 */
#define HSEM_ISR_ISEM31 HSEM_ISR_ISEM31_Msk /*!<semaphore 31 interrupt 0 status bit. */
/******************** Bit definition for HSEM_MISR register *****************/
#define HSEM_MISR_ISEM0_Pos (0U)
#define HSEM_MISR_ISEM0_Msk (0x1U << HSEM_MISR_ISEM0_Pos) /*!< 0x00000001 */
#define HSEM_MISR_ISEM0 HSEM_MISR_ISEM0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM1_Pos (1U)
#define HSEM_MISR_ISEM1_Msk (0x1U << HSEM_MISR_ISEM1_Pos) /*!< 0x00000002 */
#define HSEM_MISR_ISEM1 HSEM_MISR_ISEM1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM2_Pos (2U)
#define HSEM_MISR_ISEM2_Msk (0x1U << HSEM_MISR_ISEM2_Pos) /*!< 0x00000004 */
#define HSEM_MISR_ISEM2 HSEM_MISR_ISEM2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM3_Pos (3U)
#define HSEM_MISR_ISEM3_Msk (0x1U << HSEM_MISR_ISEM3_Pos) /*!< 0x00000008 */
#define HSEM_MISR_ISEM3 HSEM_MISR_ISEM3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM4_Pos (4U)
#define HSEM_MISR_ISEM4_Msk (0x1U << HSEM_MISR_ISEM4_Pos) /*!< 0x00000010 */
#define HSEM_MISR_ISEM4 HSEM_MISR_ISEM4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM5_Pos (5U)
#define HSEM_MISR_ISEM5_Msk (0x1U << HSEM_MISR_ISEM5_Pos) /*!< 0x00000020 */
#define HSEM_MISR_ISEM5 HSEM_MISR_ISEM5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM6_Pos (6U)
#define HSEM_MISR_ISEM6_Msk (0x1U << HSEM_MISR_ISEM6_Pos) /*!< 0x00000040 */
#define HSEM_MISR_ISEM6 HSEM_MISR_ISEM6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM7_Pos (7U)
#define HSEM_MISR_ISEM7_Msk (0x1U << HSEM_MISR_ISEM7_Pos) /*!< 0x00000080 */
#define HSEM_MISR_ISEM7 HSEM_MISR_ISEM7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM8_Pos (8U)
#define HSEM_MISR_ISEM8_Msk (0x1U << HSEM_MISR_ISEM8_Pos) /*!< 0x00000100 */
#define HSEM_MISR_ISEM8 HSEM_MISR_ISEM8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM9_Pos (9U)
#define HSEM_MISR_ISEM9_Msk (0x1U << HSEM_MISR_ISEM9_Pos) /*!< 0x00000200 */
#define HSEM_MISR_ISEM9 HSEM_MISR_ISEM9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM10_Pos (10U)
#define HSEM_MISR_ISEM10_Msk (0x1U << HSEM_MISR_ISEM10_Pos) /*!< 0x00000400 */
#define HSEM_MISR_ISEM10 HSEM_MISR_ISEM10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM11_Pos (11U)
#define HSEM_MISR_ISEM11_Msk (0x1U << HSEM_MISR_ISEM11_Pos) /*!< 0x00000800 */
#define HSEM_MISR_ISEM11 HSEM_MISR_ISEM11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM12_Pos (12U)
#define HSEM_MISR_ISEM12_Msk (0x1U << HSEM_MISR_ISEM12_Pos) /*!< 0x00001000 */
#define HSEM_MISR_ISEM12 HSEM_MISR_ISEM12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM13_Pos (13U)
#define HSEM_MISR_ISEM13_Msk (0x1U << HSEM_MISR_ISEM13_Pos) /*!< 0x00002000 */
#define HSEM_MISR_ISEM13 HSEM_MISR_ISEM13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM14_Pos (14U)
#define HSEM_MISR_ISEM14_Msk (0x1U << HSEM_MISR_ISEM14_Pos) /*!< 0x00004000 */
#define HSEM_MISR_ISEM14 HSEM_MISR_ISEM14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM15_Pos (15U)
#define HSEM_MISR_ISEM15_Msk (0x1U << HSEM_MISR_ISEM15_Pos) /*!< 0x00008000 */
#define HSEM_MISR_ISEM15 HSEM_MISR_ISEM15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM16_Pos (16U)
#define HSEM_MISR_ISEM16_Msk (0x1U << HSEM_MISR_ISEM16_Pos) /*!< 0x00010000 */
#define HSEM_MISR_ISEM16 HSEM_MISR_ISEM16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM17_Pos (17U)
#define HSEM_MISR_ISEM17_Msk (0x1U << HSEM_MISR_ISEM17_Pos) /*!< 0x00020000 */
#define HSEM_MISR_ISEM17 HSEM_MISR_ISEM17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM18_Pos (18U)
#define HSEM_MISR_ISEM18_Msk (0x1U << HSEM_MISR_ISEM18_Pos) /*!< 0x00040000 */
#define HSEM_MISR_ISEM18 HSEM_MISR_ISEM18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM19_Pos (19U)
#define HSEM_MISR_ISEM19_Msk (0x1U << HSEM_MISR_ISEM19_Pos) /*!< 0x00080000 */
#define HSEM_MISR_ISEM19 HSEM_MISR_ISEM19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM20_Pos (20U)
#define HSEM_MISR_ISEM20_Msk (0x1U << HSEM_MISR_ISEM20_Pos) /*!< 0x00100000 */
#define HSEM_MISR_ISEM20 HSEM_MISR_ISEM20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM21_Pos (21U)
#define HSEM_MISR_ISEM21_Msk (0x1U << HSEM_MISR_ISEM21_Pos) /*!< 0x00200000 */
#define HSEM_MISR_ISEM21 HSEM_MISR_ISEM21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM22_Pos (22U)
#define HSEM_MISR_ISEM22_Msk (0x1U << HSEM_MISR_ISEM22_Pos) /*!< 0x00400000 */
#define HSEM_MISR_ISEM22 HSEM_MISR_ISEM22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM23_Pos (23U)
#define HSEM_MISR_ISEM23_Msk (0x1U << HSEM_MISR_ISEM23_Pos) /*!< 0x00800000 */
#define HSEM_MISR_ISEM23 HSEM_MISR_ISEM23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM24_Pos (24U)
#define HSEM_MISR_ISEM24_Msk (0x1U << HSEM_MISR_ISEM24_Pos) /*!< 0x01000000 */
#define HSEM_MISR_ISEM24 HSEM_MISR_ISEM24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM25_Pos (25U)
#define HSEM_MISR_ISEM25_Msk (0x1U << HSEM_MISR_ISEM25_Pos) /*!< 0x02000000 */
#define HSEM_MISR_ISEM25 HSEM_MISR_ISEM25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM26_Pos (26U)
#define HSEM_MISR_ISEM26_Msk (0x1U << HSEM_MISR_ISEM26_Pos) /*!< 0x04000000 */
#define HSEM_MISR_ISEM26 HSEM_MISR_ISEM26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM27_Pos (27U)
#define HSEM_MISR_ISEM27_Msk (0x1U << HSEM_MISR_ISEM27_Pos) /*!< 0x08000000 */
#define HSEM_MISR_ISEM27 HSEM_MISR_ISEM27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM28_Pos (28U)
#define HSEM_MISR_ISEM28_Msk (0x1U << HSEM_MISR_ISEM28_Pos) /*!< 0x10000000 */
#define HSEM_MISR_ISEM28 HSEM_MISR_ISEM28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM29_Pos (29U)
#define HSEM_MISR_ISEM29_Msk (0x1U << HSEM_MISR_ISEM29_Pos) /*!< 0x20000000 */
#define HSEM_MISR_ISEM29 HSEM_MISR_ISEM29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM30_Pos (30U)
#define HSEM_MISR_ISEM30_Msk (0x1U << HSEM_MISR_ISEM30_Pos) /*!< 0x40000000 */
#define HSEM_MISR_ISEM30 HSEM_MISR_ISEM30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
#define HSEM_MISR_ISEM31_Pos (31U)
#define HSEM_MISR_ISEM31_Msk (0x1U << HSEM_MISR_ISEM31_Pos) /*!< 0x80000000 */
#define HSEM_MISR_ISEM31 HSEM_MISR_ISEM31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
/******************** Bit definition for HSEM_CR register *****************/
#define HSEM_CR_MASTERID_Pos (8U)
#define HSEM_CR_MASTERID_Msk (0xFFU << HSEM_CR_MASTERID_Pos) /*!< 0x0000FF00 */
#define HSEM_CR_MASTERID HSEM_CR_MASTERID_Msk /*!<MasterID of semaphores to be cleared. */
#define HSEM_CR_KEY_Pos (16U)
#define HSEM_CR_KEY_Msk (0xFFFFU << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
/******************** Bit definition for HSEM_KEYR register *****************/
#define HSEM_KEYR_KEY_Pos (16U)
#define HSEM_KEYR_KEY_Msk (0xFFFFU << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
/******************************************************************************/
/* */
/* HASH */
/* */
/******************************************************************************/
/****************** Bits definition for HASH_CR register ********************/
#define HASH_CR_INIT_Pos (2U)
#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
#define HASH_CR_INIT HASH_CR_INIT_Msk
#define HASH_CR_DMAE_Pos (3U)
#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
#define HASH_CR_DMAE HASH_CR_DMAE_Msk
#define HASH_CR_DATATYPE_Pos (4U)
#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
#define HASH_CR_MODE_Pos (6U)
#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
#define HASH_CR_MODE HASH_CR_MODE_Msk
#define HASH_CR_ALGO_Pos (7U)
#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
#define HASH_CR_ALGO HASH_CR_ALGO_Msk
#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
#define HASH_CR_NBW_Pos (8U)
#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
#define HASH_CR_NBW HASH_CR_NBW_Msk
#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos (12U)
#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
#define HASH_CR_DINNE HASH_CR_DINNE_Msk
#define HASH_CR_MDMAT_Pos (13U)
#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
#define HASH_CR_LKEY_Pos (16U)
#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
#define HASH_CR_LKEY HASH_CR_LKEY_Msk
/****************** Bits definition for HASH_STR register *******************/
#define HASH_STR_NBLW_Pos (0U)
#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
#define HASH_STR_NBLW HASH_STR_NBLW_Msk
#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos (8U)
#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
#define HASH_STR_DCAL HASH_STR_DCAL_Msk
/****************** Bits definition for HASH_IMR register *******************/
#define HASH_IMR_DINIE_Pos (0U)
#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
#define HASH_IMR_DCIE_Pos (1U)
#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS_Pos (0U)
#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
#define HASH_SR_DINIS HASH_SR_DINIS_Msk
#define HASH_SR_DCIS_Pos (1U)
#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
#define HASH_SR_DCIS HASH_SR_DCIS_Msk
#define HASH_SR_DMAS_Pos (2U)
#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
#define HASH_SR_DMAS HASH_SR_DMAS_Msk
#define HASH_SR_BUSY_Pos (3U)
#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
#define HASH_SR_BUSY HASH_SR_BUSY_Msk
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* JPEG Encoder/Decoder */
/* */
/******************************************************************************/
/******************** Bit definition for CONFR0 register ********************/
#define JPEG_CONFR0_START_Pos (0U)
#define JPEG_CONFR0_START_Msk (0x1U << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
/******************** Bit definition for CONFR1 register ********************/
#define JPEG_CONFR1_NF_Pos (0U)
#define JPEG_CONFR1_NF_Msk (0x3U << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
#define JPEG_CONFR1_NF_0 (0x1U << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
#define JPEG_CONFR1_NF_1 (0x2U << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
#define JPEG_CONFR1_DE_Pos (3U)
#define JPEG_CONFR1_DE_Msk (0x1U << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
#define JPEG_CONFR1_COLORSPACE_Pos (4U)
#define JPEG_CONFR1_COLORSPACE_Msk (0x3U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
#define JPEG_CONFR1_COLORSPACE_0 (0x1U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
#define JPEG_CONFR1_COLORSPACE_1 (0x2U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
#define JPEG_CONFR1_NS_Pos (6U)
#define JPEG_CONFR1_NS_Msk (0x3U << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
#define JPEG_CONFR1_NS_0 (0x1U << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
#define JPEG_CONFR1_NS_1 (0x2U << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
#define JPEG_CONFR1_HDR_Pos (8U)
#define JPEG_CONFR1_HDR_Msk (0x1U << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
#define JPEG_CONFR1_YSIZE_Pos (16U)
#define JPEG_CONFR1_YSIZE_Msk (0xFFFFU << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
/******************** Bit definition for CONFR2 register ********************/
#define JPEG_CONFR2_NMCU_Pos (0U)
#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFU << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
/******************** Bit definition for CONFR3 register ********************/
#define JPEG_CONFR3_XSIZE_Pos (16U)
#define JPEG_CONFR3_XSIZE_Msk (0xFFFFU << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
/******************** Bit definition for CONFR4 register ********************/
#define JPEG_CONFR4_HD_Pos (0U)
#define JPEG_CONFR4_HD_Msk (0x1U << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR4_HA_Pos (1U)
#define JPEG_CONFR4_HA_Msk (0x1U << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR4_QT_Pos (2U)
#define JPEG_CONFR4_QT_Msk (0x3U << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR4_QT_0 (0x1U << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR4_QT_1 (0x2U << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR4_NB_Pos (4U)
#define JPEG_CONFR4_NB_Msk (0xFU << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR4_NB_0 (0x1U << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR4_NB_1 (0x2U << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR4_NB_2 (0x4U << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR4_NB_3 (0x8U << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR4_VSF_Pos (8U)
#define JPEG_CONFR4_VSF_Msk (0xFU << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
#define JPEG_CONFR4_VSF_0 (0x1U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR4_VSF_1 (0x2U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR4_VSF_2 (0x4U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR4_VSF_3 (0x8U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR4_HSF_Pos (12U)
#define JPEG_CONFR4_HSF_Msk (0xFU << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
#define JPEG_CONFR4_HSF_0 (0x1U << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR4_HSF_1 (0x2U << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR4_HSF_2 (0x4U << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR4_HSF_3 (0x8U << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR5 register ********************/
#define JPEG_CONFR5_HD_Pos (0U)
#define JPEG_CONFR5_HD_Msk (0x1U << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR5_HA_Pos (1U)
#define JPEG_CONFR5_HA_Msk (0x1U << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR5_QT_Pos (2U)
#define JPEG_CONFR5_QT_Msk (0x3U << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR5_QT_0 (0x1U << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR5_QT_1 (0x2U << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR5_NB_Pos (4U)
#define JPEG_CONFR5_NB_Msk (0xFU << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR5_NB_0 (0x1U << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR5_NB_1 (0x2U << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR5_NB_2 (0x4U << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR5_NB_3 (0x8U << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR5_VSF_Pos (8U)
#define JPEG_CONFR5_VSF_Msk (0xFU << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR5_VSF_0 (0x1U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR5_VSF_1 (0x2U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR5_VSF_2 (0x4U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR5_VSF_3 (0x8U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR5_HSF_Pos (12U)
#define JPEG_CONFR5_HSF_Msk (0xFU << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR5_HSF_0 (0x1U << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR5_HSF_1 (0x2U << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR5_HSF_2 (0x4U << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR5_HSF_3 (0x8U << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR6 register ********************/
#define JPEG_CONFR6_HD_Pos (0U)
#define JPEG_CONFR6_HD_Msk (0x1U << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR6_HA_Pos (1U)
#define JPEG_CONFR6_HA_Msk (0x1U << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR6_QT_Pos (2U)
#define JPEG_CONFR6_QT_Msk (0x3U << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR6_QT_0 (0x1U << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR6_QT_1 (0x2U << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR6_NB_Pos (4U)
#define JPEG_CONFR6_NB_Msk (0xFU << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR6_NB_0 (0x1U << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR6_NB_1 (0x2U << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR6_NB_2 (0x4U << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR6_NB_3 (0x8U << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR6_VSF_Pos (8U)
#define JPEG_CONFR6_VSF_Msk (0xFU << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR6_VSF_0 (0x1U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR6_VSF_1 (0x2U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR6_VSF_2 (0x4U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR6_VSF_3 (0x8U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR6_HSF_Pos (12U)
#define JPEG_CONFR6_HSF_Msk (0xFU << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR6_HSF_0 (0x1U << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR6_HSF_1 (0x2U << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR6_HSF_2 (0x4U << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR6_HSF_3 (0x8U << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR7 register ********************/
#define JPEG_CONFR7_HD_Pos (0U)
#define JPEG_CONFR7_HD_Msk (0x1U << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR7_HA_Pos (1U)
#define JPEG_CONFR7_HA_Msk (0x1U << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR7_QT_Pos (2U)
#define JPEG_CONFR7_QT_Msk (0x3U << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR7_QT_0 (0x1U << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR7_QT_1 (0x2U << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR7_NB_Pos (4U)
#define JPEG_CONFR7_NB_Msk (0xFU << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR7_NB_0 (0x1U << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR7_NB_1 (0x2U << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR7_NB_2 (0x4U << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR7_NB_3 (0x8U << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR7_VSF_Pos (8U)
#define JPEG_CONFR7_VSF_Msk (0xFU << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR7_VSF_0 (0x1U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR7_VSF_1 (0x2U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR7_VSF_2 (0x4U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR7_VSF_3 (0x8U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR7_HSF_Pos (12U)
#define JPEG_CONFR7_HSF_Msk (0xFU << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR7_HSF_0 (0x1U << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR7_HSF_1 (0x2U << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR7_HSF_2 (0x4U << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR7_HSF_3 (0x8U << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CR register ********************/
#define JPEG_CR_JCEN_Pos (0U)
#define JPEG_CR_JCEN_Msk (0x1U << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
#define JPEG_CR_IFTIE_Pos (1U)
#define JPEG_CR_IFTIE_Msk (0x1U << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
#define JPEG_CR_IFNFIE_Pos (2U)
#define JPEG_CR_IFNFIE_Msk (0x1U << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
#define JPEG_CR_OFTIE_Pos (3U)
#define JPEG_CR_OFTIE_Msk (0x1U << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
#define JPEG_CR_OFNEIE_Pos (4U)
#define JPEG_CR_OFNEIE_Msk (0x1U << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
#define JPEG_CR_EOCIE_Pos (5U)
#define JPEG_CR_EOCIE_Msk (0x1U << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
#define JPEG_CR_HPDIE_Pos (6U)
#define JPEG_CR_HPDIE_Msk (0x1U << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
#define JPEG_CR_IFF_Pos (13U)
#define JPEG_CR_IFF_Msk (0x1U << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
#define JPEG_CR_OFF_Pos (14U)
#define JPEG_CR_OFF_Msk (0x1U << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
/******************** Bit definition for SR register ********************/
#define JPEG_SR_IFTF_Pos (1U)
#define JPEG_SR_IFTF_Msk (0x1U << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
#define JPEG_SR_IFNFF_Pos (2U)
#define JPEG_SR_IFNFF_Msk (0x1U << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
#define JPEG_SR_OFTF_Pos (3U)
#define JPEG_SR_OFTF_Msk (0x1U << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
#define JPEG_SR_OFNEF_Pos (4U)
#define JPEG_SR_OFNEF_Msk (0x1U << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
#define JPEG_SR_EOCF_Pos (5U)
#define JPEG_SR_EOCF_Msk (0x1U << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_SR_HPDF_Pos (6U)
#define JPEG_SR_HPDF_Msk (0x1U << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_SR_COF_Pos (7U)
#define JPEG_SR_COF_Msk (0x1U << JPEG_SR_COF_Pos) /*!< 0x00000080 */
#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
/******************** Bit definition for CFR register ********************/
#define JPEG_CFR_CEOCF_Pos (4U)
#define JPEG_CFR_CEOCF_Msk (0x1U << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
#define JPEG_CFR_CHPDF_Pos (5U)
#define JPEG_CFR_CHPDF_Msk (0x1U << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
/******************** Bit definition for DIR register ********************/
#define JPEG_DIR_DATAIN_Pos (0U)
#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFU << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
/******************** Bit definition for DOR register ********************/
#define JPEG_DOR_DATAOUT_Pos (0U)
#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFU << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* MDMA */
/* */
/******************************************************************************/
/******************** Bit definition for MDMA_GISR0 register ****************/
#define MDMA_GISR0_GIF0_Pos (0U)
#define MDMA_GISR0_GIF0_Msk (0x1U << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
#define MDMA_GISR0_GIF1_Pos (1U)
#define MDMA_GISR0_GIF1_Msk (0x1U << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
#define MDMA_GISR0_GIF2_Pos (2U)
#define MDMA_GISR0_GIF2_Msk (0x1U << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
#define MDMA_GISR0_GIF3_Pos (3U)
#define MDMA_GISR0_GIF3_Msk (0x1U << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
#define MDMA_GISR0_GIF4_Pos (4U)
#define MDMA_GISR0_GIF4_Msk (0x1U << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
#define MDMA_GISR0_GIF5_Pos (5U)
#define MDMA_GISR0_GIF5_Msk (0x1U << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
#define MDMA_GISR0_GIF6_Pos (6U)
#define MDMA_GISR0_GIF6_Msk (0x1U << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
#define MDMA_GISR0_GIF7_Pos (7U)
#define MDMA_GISR0_GIF7_Msk (0x1U << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
#define MDMA_GISR0_GIF8_Pos (8U)
#define MDMA_GISR0_GIF8_Msk (0x1U << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
#define MDMA_GISR0_GIF9_Pos (9U)
#define MDMA_GISR0_GIF9_Msk (0x1U << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
#define MDMA_GISR0_GIF10_Pos (10U)
#define MDMA_GISR0_GIF10_Msk (0x1U << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
#define MDMA_GISR0_GIF11_Pos (11U)
#define MDMA_GISR0_GIF11_Msk (0x1U << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
#define MDMA_GISR0_GIF12_Pos (12U)
#define MDMA_GISR0_GIF12_Msk (0x1U << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
#define MDMA_GISR0_GIF13_Pos (13U)
#define MDMA_GISR0_GIF13_Msk (0x1U << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
#define MDMA_GISR0_GIF14_Pos (14U)
#define MDMA_GISR0_GIF14_Msk (0x1U << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
#define MDMA_GISR0_GIF15_Pos (15U)
#define MDMA_GISR0_GIF15_Msk (0x1U << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
/******************** Bit definition for MDMA_CxISR register ****************/
#define MDMA_CISR_TEIF_Pos (0U)
#define MDMA_CISR_TEIF_Msk (0x1U << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
#define MDMA_CISR_CTCIF_Pos (1U)
#define MDMA_CISR_CTCIF_Msk (0x1U << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
#define MDMA_CISR_BRTIF_Pos (2U)
#define MDMA_CISR_BRTIF_Msk (0x1U << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
#define MDMA_CISR_BTIF_Pos (3U)
#define MDMA_CISR_BTIF_Msk (0x1U << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
#define MDMA_CISR_TCIF_Pos (4U)
#define MDMA_CISR_TCIF_Msk (0x1U << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1U << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
#define MDMA_CIFCR_CTEIF_Msk (0x1U << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
#define MDMA_CIFCR_CCTCIF_Pos (1U)
#define MDMA_CIFCR_CCTCIF_Msk (0x1U << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
#define MDMA_CIFCR_CBRTIF_Pos (2U)
#define MDMA_CIFCR_CBRTIF_Msk (0x1U << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
#define MDMA_CIFCR_CBTIF_Pos (3U)
#define MDMA_CIFCR_CBTIF_Msk (0x1U << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
#define MDMA_CIFCR_CLTCIF_Pos (4U)
#define MDMA_CIFCR_CLTCIF_Msk (0x1U << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
/******************** Bit definition for MDMA_CxESR register ****************/
#define MDMA_CESR_TEA_Pos (0U)
#define MDMA_CESR_TEA_Msk (0x7FU << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
#define MDMA_CESR_TED_Pos (7U)
#define MDMA_CESR_TED_Msk (0x1U << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
#define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
#define MDMA_CESR_TELD_Pos (8U)
#define MDMA_CESR_TELD_Msk (0x1U << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
#define MDMA_CESR_TEMD_Pos (9U)
#define MDMA_CESR_TEMD_Msk (0x1U << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
#define MDMA_CESR_ASE_Pos (10U)
#define MDMA_CESR_ASE_Msk (0x1U << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
#define MDMA_CESR_BSE_Pos (11U)
#define MDMA_CESR_BSE_Msk (0x1U << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
/******************** Bit definition for MDMA_CxCR register ****************/
#define MDMA_CCR_EN_Pos (0U)
#define MDMA_CCR_EN_Msk (0x1U << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
#define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
#define MDMA_CCR_TEIE_Pos (1U)
#define MDMA_CCR_TEIE_Msk (0x1U << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define MDMA_CCR_CTCIE_Pos (2U)
#define MDMA_CCR_CTCIE_Msk (0x1U << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
#define MDMA_CCR_BRTIE_Pos (3U)
#define MDMA_CCR_BRTIE_Msk (0x1U << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
#define MDMA_CCR_BTIE_Pos (4U)
#define MDMA_CCR_BTIE_Msk (0x1U << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
#define MDMA_CCR_TCIE_Pos (5U)
#define MDMA_CCR_TCIE_Msk (0x1U << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
#define MDMA_CCR_PL_Pos (6U)
#define MDMA_CCR_PL_Msk (0x3U << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
#define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
#define MDMA_CCR_PL_0 (0x1U << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
#define MDMA_CCR_PL_1 (0x2U << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1U << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1U << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1U << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1U << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
/******************** Bit definition for MDMA_CxTCR register ****************/
#define MDMA_CTCR_SINC_Pos (0U)
#define MDMA_CTCR_SINC_Msk (0x3U << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
#define MDMA_CTCR_SINC_0 (0x1U << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
#define MDMA_CTCR_SINC_1 (0x2U << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
#define MDMA_CTCR_DINC_Pos (2U)
#define MDMA_CTCR_DINC_Msk (0x3U << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
#define MDMA_CTCR_DINC_0 (0x1U << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
#define MDMA_CTCR_DINC_1 (0x2U << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
#define MDMA_CTCR_SSIZE_Pos (4U)
#define MDMA_CTCR_SSIZE_Msk (0x3U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
#define MDMA_CTCR_SSIZE_0 (0x1U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
#define MDMA_CTCR_SSIZE_1 (0x2U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
#define MDMA_CTCR_DSIZE_Pos (6U)
#define MDMA_CTCR_DSIZE_Msk (0x3U << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
#define MDMA_CTCR_DSIZE_0 (0x1U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
#define MDMA_CTCR_DSIZE_1 (0x2U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
#define MDMA_CTCR_SINCOS_Pos (8U)
#define MDMA_CTCR_SINCOS_Msk (0x3U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
#define MDMA_CTCR_SINCOS_0 (0x1U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
#define MDMA_CTCR_SINCOS_1 (0x2U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
#define MDMA_CTCR_DINCOS_Pos (10U)
#define MDMA_CTCR_DINCOS_Msk (0x3U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
#define MDMA_CTCR_DINCOS_0 (0x1U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
#define MDMA_CTCR_DINCOS_1 (0x2U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
#define MDMA_CTCR_SBURST_Pos (12U)
#define MDMA_CTCR_SBURST_Msk (0x7U << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
#define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
#define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */
#define MDMA_CTCR_DBURST_Pos (15U)
#define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
#define MDMA_CTCR_DBURST_0 (0x1U << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
#define MDMA_CTCR_DBURST_1 (0x2U << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
#define MDMA_CTCR_DBURST_2 (0x4U << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
#define MDMA_CTCR_TLEN_Pos (18U)
#define MDMA_CTCR_TLEN_Msk (0x7FU << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
#define MDMA_CTCR_PKE_Pos (25U)
#define MDMA_CTCR_PKE_Msk (0x1U << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3U << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
#define MDMA_CTCR_PAM_0 (0x1U << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2U << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
#define MDMA_CTCR_TRGM_Msk (0x3U << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
#define MDMA_CTCR_TRGM_0 (0x1U << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
#define MDMA_CTCR_TRGM_1 (0x2U << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
#define MDMA_CTCR_SWRM_Pos (30U)
#define MDMA_CTCR_SWRM_Msk (0x1U << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
#define MDMA_CTCR_BWM_Pos (31U)
#define MDMA_CTCR_BWM_Msk (0x1U << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
/******************** Bit definition for MDMA_CxBNDTR register ****************/
#define MDMA_CBNDTR_BNDT_Pos (0U)
#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFU << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
#define MDMA_CBNDTR_BRSUM_Pos (18U)
#define MDMA_CBNDTR_BRSUM_Msk (0x1U << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
#define MDMA_CBNDTR_BRDUM_Pos (19U)
#define MDMA_CBNDTR_BRDUM_Msk (0x1U << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
#define MDMA_CBNDTR_BRC_Pos (20U)
#define MDMA_CBNDTR_BRC_Msk (0xFFFU << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
/******************** Bit definition for MDMA_CxSAR register ****************/
#define MDMA_CSAR_SAR_Pos (0U)
#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFU << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
/******************** Bit definition for MDMA_CxDAR register ****************/
#define MDMA_CDAR_DAR_Pos (0U)
#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFU << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
/******************** Bit definition for MDMA_CxBRUR ************************/
#define MDMA_CBRUR_SUV_Pos (0U)
#define MDMA_CBRUR_SUV_Msk (0xFFFFU << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
#define MDMA_CBRUR_DUV_Pos (16U)
#define MDMA_CBRUR_DUV_Msk (0xFFFFU << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
/******************** Bit definition for MDMA_CxLAR *************************/
#define MDMA_CLAR_LAR_Pos (0U)
#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFU << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
/******************** Bit definition for MDMA_CxTBR) ************************/
#define MDMA_CTBR_TSEL_Pos (0U)
#define MDMA_CTBR_TSEL_Msk (0xFFU << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
#define MDMA_CTBR_SBUS_Pos (16U)
#define MDMA_CTBR_SBUS_Msk (0x1U << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
#define MDMA_CTBR_DBUS_Pos (17U)
#define MDMA_CTBR_DBUS_Msk (0x1U << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
/******************** Bit definition for MDMA_CxMAR) ************************/
#define MDMA_CMAR_MAR_Pos (0U)
#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFU << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
/******************** Bit definition for MDMA_CxMDR) ************************/
#define MDMA_CMDR_MDR_Pos (0U)
#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFU << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Mask Data */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_OPAHSM_Pos (8U)
#define OPAMP_CSR_OPAHSM_Msk (0x1U << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_USERTRIM_Pos (18U)
#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_TSTREF_Pos (29U)
#define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP_CSR_CALOUT_Pos (30U)
#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
/********************* Bit definition for OPAMP1_CSR register ***************/
#define OPAMP1_CSR_OPAEN_Pos (0U)
#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
#define OPAMP1_CSR_FORCEVP_Pos (1U)
#define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP1_CSR_VPSEL_Pos (2U)
#define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP1_CSR_VMSEL_Pos (5U)
#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP1_CSR_OPAHSM_Pos (8U)
#define OPAMP1_CSR_OPAHSM_Msk (0x1U << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
#define OPAMP1_CSR_CALON_Pos (11U)
#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP1_CSR_CALSEL_Pos (12U)
#define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP1_CSR_PGGAIN_Pos (14U)
#define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
#define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP1_CSR_USERTRIM_Pos (18U)
#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP1_CSR_TSTREF_Pos (29U)
#define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP1_CSR_CALOUT_Pos (30U)
#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
/********************* Bit definition for OPAMP2_CSR register ***************/
#define OPAMP2_CSR_OPAEN_Pos (0U)
#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
#define OPAMP2_CSR_FORCEVP_Pos (1U)
#define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP2_CSR_VPSEL_Pos (2U)
#define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP2_CSR_VMSEL_Pos (5U)
#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP2_CSR_OPAHSM_Pos (8U)
#define OPAMP2_CSR_OPAHSM_Msk (0x1U << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
#define OPAMP2_CSR_CALON_Pos (11U)
#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP2_CSR_CALSEL_Pos (12U)
#define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP2_CSR_PGGAIN_Pos (14U)
#define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
#define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP2_CSR_USERTRIM_Pos (18U)
#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP2_CSR_TSTREF_Pos (29U)
#define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP2_CSR_CALOUT_Pos (30U)
#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
/******************* Bit definition for OPAMP_OTR register ******************/
#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP1_OTR register ******************/
#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP2_OTR register ******************/
#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP_HSOTR register ****************/
#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP1_HSOTR register ****************/
#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP2_HSOTR register ****************/
#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_ALS_Pos (17U)
#define PWR_CR1_ALS_Msk (0x3U << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
#define PWR_CR1_ALS_0 (0x1U << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
#define PWR_CR1_ALS_1 (0x2U << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
#define PWR_CR1_AVDEN_Pos (16U)
#define PWR_CR1_AVDEN_Msk (0x1U << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
#define PWR_CR1_SVOS_Pos (14U)
#define PWR_CR1_SVOS_Msk (0x3U << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */
#define PWR_CR1_SVOS_0 (0x1U << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
#define PWR_CR1_SVOS_1 (0x2U << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
#define PWR_CR1_RLPSN_Pos (10U)
#define PWR_CR1_RLPSN_Msk (0x1U << PWR_CR1_RLPSN_Pos) /*!< 0x00000400 */
#define PWR_CR1_RLPSN PWR_CR1_RLPSN_Msk /*!< RAM low power mode disable in STOP. */
#define PWR_CR1_FLPS_Pos (9U)
#define PWR_CR1_FLPS_Msk (0x1U << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_PLS_Pos (5U)
#define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
#define PWR_CR1_PLS_0 (0x1U << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
#define PWR_CR1_PLS_1 (0x2U << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
#define PWR_CR1_PLS_2 (0x4U << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
#define PWR_CR1_PVDEN_Pos (4U)
#define PWR_CR1_PVDEN_Msk (0x1U << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */
#define PWR_CR1_LPDS_Pos (0U)
#define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
/*!< PVD level configuration */
#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
#define PWR_CR1_PLS_LEV1_Pos (5U)
#define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR1_PLS_LEV2_Pos (6U)
#define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR1_PLS_LEV3_Pos (5U)
#define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR1_PLS_LEV4_Pos (7U)
#define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR1_PLS_LEV5_Pos (5U)
#define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR1_PLS_LEV6_Pos (6U)
#define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR1_PLS_LEV7_Pos (5U)
#define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
/*!< AVD level configuration */
#define PWR_CR1_ALS_LEV0 ((uint32_t)0x00000000U) /*!< AVD level 0 */
#define PWR_CR1_ALS_LEV1_Pos (17U)
#define PWR_CR1_ALS_LEV1_Msk (0x1U << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
#define PWR_CR1_ALS_LEV2_Pos (18U)
#define PWR_CR1_ALS_LEV2_Msk (0x1U << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
#define PWR_CR1_ALS_LEV3_Pos (17U)
#define PWR_CR1_ALS_LEV3_Msk (0x3U << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
/******************** Bit definition for PWR_CSR1 register ********************/
#define PWR_CSR1_AVDO_Pos (16U)
#define PWR_CSR1_AVDO_Msk (0x1U << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
#define PWR_CSR1_ACTVOS_Pos (14U)
#define PWR_CSR1_ACTVOS_Msk (0x3U << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
#define PWR_CSR1_ACTVOS_0 (0x1U << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
#define PWR_CSR1_ACTVOS_1 (0x2U << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
#define PWR_CSR1_ACTVOSRDY_Pos (13U)
#define PWR_CSR1_ACTVOSRDY_Msk (0x1U << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
#define PWR_CSR1_PVDO_Pos (4U)
#define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
/******************** Bit definition for PWR_CR2 register ********************/
#define PWR_CR2_TEMPH_Pos (23U)
#define PWR_CR2_TEMPH_Msk (0x1U << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
#define PWR_CR2_TEMPL_Pos (22U)
#define PWR_CR2_TEMPL_Msk (0x1U << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
#define PWR_CR2_VBATH_Pos (21U)
#define PWR_CR2_VBATH_Msk (0x1U << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
#define PWR_CR2_VBATL_Pos (20U)
#define PWR_CR2_VBATL_Msk (0x1U << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
#define PWR_CR2_BRRDY_Pos (16U)
#define PWR_CR2_BRRDY_Msk (0x1U << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
#define PWR_CR2_MONEN_Pos (4U)
#define PWR_CR2_MONEN_Msk (0x1U << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
#define PWR_CR2_BREN_Pos (0U)
#define PWR_CR2_BREN_Msk (0x1U << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_USB33RDY_Pos (26U)
#define PWR_CR3_USB33RDY_Msk (0x1U << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
#define PWR_CR3_USBREGEN_Pos (25U)
#define PWR_CR3_USBREGEN_Msk (0x1U << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
#define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
#define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
#define PWR_CR3_VBE_Pos (8U)
#define PWR_CR3_VBE_Msk (0x1U << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
#define PWR_CR3_SCUEN_Pos (2U)
#define PWR_CR3_SCUEN_Msk (0x1U << PWR_CR3_SCUEN_Pos) /*!< 0x00000004 */
#define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk /*!< Supply configuration update enable */
#define PWR_CR3_LDOEN_Pos (1U)
#define PWR_CR3_LDOEN_Msk (0x1U << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
#define PWR_CR3_BYPASS_Pos (0U)
#define PWR_CR3_BYPASS_Msk (0x1U << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
/******************** Bit definition for PWR_CPUCR register ********************/
#define PWR_CPUCR_RUN_D3_Pos (11U)
#define PWR_CPUCR_RUN_D3_Msk (0x1U << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
#define PWR_CPUCR_CSSF_Pos (9U)
#define PWR_CPUCR_CSSF_Msk (0x1U << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU STANDBY, STOP and HOLD flags */
#define PWR_CPUCR_SBF_D2_Pos (8U)
#define PWR_CPUCR_SBF_D2_Msk (0x1U << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
#define PWR_CPUCR_SBF_D1_Pos (7U)
#define PWR_CPUCR_SBF_D1_Msk (0x1U << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
#define PWR_CPUCR_SBF_Pos (6U)
#define PWR_CPUCR_SBF_Msk (0x1U << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
#define PWR_CPUCR_STOPF_Pos (5U)
#define PWR_CPUCR_STOPF_Msk (0x1U << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
#define PWR_CPUCR_PDDS_D3_Pos (2U)
#define PWR_CPUCR_PDDS_D3_Msk (0x1U << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
#define PWR_CPUCR_PDDS_D2_Pos (1U)
#define PWR_CPUCR_PDDS_D2_Msk (0x1U << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
#define PWR_CPUCR_PDDS_D1_Pos (0U)
#define PWR_CPUCR_PDDS_D1_Msk (0x1U << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
/******************** Bit definition for PWR_D3CR register ********************/
#define PWR_D3CR_VOS_Pos (14U)
#define PWR_D3CR_VOS_Msk (0x3U << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
#define PWR_D3CR_VOS_0 (0x1U << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
#define PWR_D3CR_VOS_1 (0x2U << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
#define PWR_D3CR_VOSRDY_Pos (13U)
#define PWR_D3CR_VOSRDY_Msk (0x1U << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
/******************** Bit definition for PWR_WKUPCR register ********************/
#define PWR_WKUPCR_WKUPC6_Pos (5U)
#define PWR_WKUPCR_WKUPC6_Msk (0x1U << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
#define PWR_WKUPCR_WKUPC5_Pos (4U)
#define PWR_WKUPCR_WKUPC5_Msk (0x1U << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
#define PWR_WKUPCR_WKUPC4_Pos (3U)
#define PWR_WKUPCR_WKUPC4_Msk (0x1U << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
#define PWR_WKUPCR_WKUPC3_Pos (2U)
#define PWR_WKUPCR_WKUPC3_Msk (0x1U << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
#define PWR_WKUPCR_WKUPC2_Pos (1U)
#define PWR_WKUPCR_WKUPC2_Msk (0x1U << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
#define PWR_WKUPCR_WKUPC1_Pos (0U)
#define PWR_WKUPCR_WKUPC1_Msk (0x1U << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
/******************** Bit definition for PWR_WKUPFR register ********************/
#define PWR_WKUPFR_WKUPF6_Pos (5U)
#define PWR_WKUPFR_WKUPF6_Msk (0x1U << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
#define PWR_WKUPFR_WKUPF5_Pos (4U)
#define PWR_WKUPFR_WKUPF5_Msk (0x1U << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
#define PWR_WKUPFR_WKUPF4_Pos (3U)
#define PWR_WKUPFR_WKUPF4_Msk (0x1U << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
#define PWR_WKUPFR_WKUPF3_Pos (2U)
#define PWR_WKUPFR_WKUPF3_Msk (0x1U << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
#define PWR_WKUPFR_WKUPF2_Pos (1U)
#define PWR_WKUPFR_WKUPF2_Msk (0x1U << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
#define PWR_WKUPFR_WKUPF1_Pos (0U)
#define PWR_WKUPFR_WKUPF1_Msk (0x1U << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
/******************** Bit definition for PWR_WKUPEPR register ********************/
#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1U << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2U << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1U << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2U << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1U << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2U << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1U << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2U << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1U << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2U << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3U << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1U << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2U << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
#define PWR_WKUPEPR_WKUPP_6 ((uint32_t)0x00002000U) /*!< Wakeup Pin Polarity for WKUP6 */
#define PWR_WKUPEPR_WKUPP_5 ((uint32_t)0x00001000U) /*!< Wakeup Pin Polarity for WKUP5 */
#define PWR_WKUPEPR_WKUPP_4 ((uint32_t)0x00000800U) /*!< Wakeup Pin Polarity for WKUP4 */
#define PWR_WKUPEPR_WKUPP_3 ((uint32_t)0x00000400U) /*!< Wakeup Pin Polarity for WKUP3 */
#define PWR_WKUPEPR_WKUPP_2 ((uint32_t)0x00000200U) /*!< Wakeup Pin Polarity for WKUP2 */
#define PWR_WKUPEPR_WKUPP_1 ((uint32_t)0x00000100U) /*!< Wakeup Pin Polarity for WKUP1 */
#define PWR_WKUPEPR_WKUPEN_6 ((uint32_t)0x00000020U) /*!< Enable Wakeup Pin WKUP6 */
#define PWR_WKUPEPR_WKUPEN_5 ((uint32_t)0x00000010U) /*!< Enable Wakeup Pin WKUP5 */
#define PWR_WKUPEPR_WKUPEN_4 ((uint32_t)0x00000008U) /*!< Enable Wakeup Pin WKUP4 */
#define PWR_WKUPEPR_WKUPEN_3 ((uint32_t)0x00000004U) /*!< Enable Wakeup Pin WKUP3 */
#define PWR_WKUPEPR_WKUPEN_2 ((uint32_t)0x00000002U) /*!< Enable Wakeup Pin WKUP2 */
#define PWR_WKUPEPR_WKUPEN_1 ((uint32_t)0x00000001U) /*!< Enable Wakeup Pin WKUP1 */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
#define RCC_CR_HSIKERON_Pos (1U)
#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (2U)
#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
#define RCC_CR_HSIDIV_Pos (3U)
#define RCC_CR_HSIDIV_Msk (0x3U << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
#define RCC_CR_HSIDIV_1 (0x0U << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
#define RCC_CR_HSIDIV_2 (0x1U << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
#define RCC_CR_HSIDIV_4 (0x2U << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
#define RCC_CR_HSIDIV_8 (0x3U << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
#define RCC_CR_HSIDIVF_Pos (5U)
#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
#define RCC_CR_CSION_Pos (7U)
#define RCC_CR_CSION_Msk (0x1U << RCC_CR_CSION_Pos) /*!< 0x00000080 */
#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
#define RCC_CR_CSIRDY_Pos (8U)
#define RCC_CR_CSIRDY_Msk (0x1U << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
#define RCC_CR_CSIKERON_Pos (9U)
#define RCC_CR_CSIKERON_Msk (0x1U << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
#define RCC_CR_HSI48ON_Pos (12U)
#define RCC_CR_HSI48ON_Msk (0x1U << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
#define RCC_CR_HSI48RDY_Pos (13U)
#define RCC_CR_HSI48RDY_Msk (0x1U << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
#define RCC_CR_D1CKRDY_Pos (14U)
#define RCC_CR_D1CKRDY_Msk (0x1U << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
#define RCC_CR_D2CKRDY_Pos (15U)
#define RCC_CR_D2CKRDY_Msk (0x1U << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
#define RCC_CR_CSSHSEON_Pos (19U)
#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
#define RCC_CR_PLL1ON_Pos (24U)
#define RCC_CR_PLL1ON_Msk (0x1U << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
#define RCC_CR_PLL1RDY_Pos (25U)
#define RCC_CR_PLL1RDY_Msk (0x1U << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
#define RCC_CR_PLL2RDY_Pos (27U)
#define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
#define RCC_CR_PLL3RDY_Pos (29U)
#define RCC_CR_PLL3RDY_Msk (0x1U << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
/*Legacy */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (0U)
#define RCC_ICSCR_HSICAL_Msk (0xFFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000FFF */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[11:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x001U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
#define RCC_ICSCR_HSICAL_1 (0x002U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
#define RCC_ICSCR_HSICAL_2 (0x004U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
#define RCC_ICSCR_HSICAL_3 (0x008U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
#define RCC_ICSCR_HSICAL_4 (0x010U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
#define RCC_ICSCR_HSICAL_5 (0x020U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
#define RCC_ICSCR_HSICAL_6 (0x040U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
#define RCC_ICSCR_HSICAL_7 (0x080U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
#define RCC_ICSCR_HSICAL_8 (0x100U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000100 */
#define RCC_ICSCR_HSICAL_9 (0x200U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000200 */
#define RCC_ICSCR_HSICAL_10 (0x400U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000400 */
#define RCC_ICSCR_HSICAL_11 (0x800U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000800 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (12U)
#define RCC_ICSCR_HSITRIM_Msk (0x3FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x0003F000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[5:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00008000 */
#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00020000 */
/*!< CSICAL configuration */
#define RCC_ICSCR_CSICAL_Pos (18U)
#define RCC_ICSCR_CSICAL_Msk (0xFFU << RCC_ICSCR_CSICAL_Pos) /*!< 0x03FC0000 */
#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_Msk /*!< CSICAL[7:0] bits */
#define RCC_ICSCR_CSICAL_0 (0x01U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_CSICAL_1 (0x02U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_CSICAL_2 (0x04U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_CSICAL_3 (0x08U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_CSICAL_4 (0x10U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_CSICAL_5 (0x20U << RCC_ICSCR_CSICAL_Pos) /*!< 0x00800000 */
#define RCC_ICSCR_CSICAL_6 (0x40U << RCC_ICSCR_CSICAL_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_CSICAL_7 (0x80U << RCC_ICSCR_CSICAL_Pos) /*!< 0x02000000 */
/*!< CSITRIM configuration */
#define RCC_ICSCR_CSITRIM_Pos (26U)
#define RCC_ICSCR_CSITRIM_Msk (0x1FU << RCC_ICSCR_CSITRIM_Pos) /*!< 0x7C000000 */
#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_Msk /*!< CSITRIM[4:0] bits */
#define RCC_ICSCR_CSITRIM_0 (0x01U << RCC_ICSCR_CSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_CSITRIM_1 (0x02U << RCC_ICSCR_CSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_CSITRIM_2 (0x04U << RCC_ICSCR_CSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_CSITRIM_3 (0x08U << RCC_ICSCR_CSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_CSITRIM_4 (0x10U << RCC_ICSCR_CSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CRRCR register *****************/
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (0U)
#define RCC_CRRCR_HSI48CAL_Msk (0x3FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
#define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
#define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
#define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
#define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
#define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_9 (0x200U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000007) /*!< SW[2:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define RCC_CFGR_SW_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selection as system clock */
#define RCC_CFGR_SW_CSI ((uint32_t)0x00000001) /*!< CSI selection as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selection as system clock */
#define RCC_CFGR_SW_PLL1 ((uint32_t)0x00000003) /*!< PLL1 selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x00000038) /*!< SWS[2:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define RCC_CFGR_SWS_2 ((uint32_t)0x00000020) /*!<Bit 2 */
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI used as system clock */
#define RCC_CFGR_SWS_CSI ((uint32_t)0x00000008) /*!< CSI used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000010) /*!< HSE used as system clock */
#define RCC_CFGR_SWS_PLL1 ((uint32_t)0x00000018) /*!< PLL1 used as system clock */
#define RCC_CFGR_STOPWUCK ((uint32_t)0x00000040) /*!< Wake Up from stop and CSS backup clock selection */
#define RCC_CFGR_STOPKERWUCK ((uint32_t)0x00000080) /*!< Kernel Clock Selection after a Wake Up from STOP */
/*!< RTCPRE configuration */
#define RCC_CFGR_RTCPRE ((uint32_t)0x00003F00)
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00000100)
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00000200)
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00000400)
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00000800)
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00001000)
#define RCC_CFGR_RTCPRE_5 ((uint32_t)0x00002000)
#define RCC_CFGR_HRTIMSEL ((uint32_t)0x00004000)
#define RCC_CFGR_TIMPRE ((uint32_t)0x00008000)
/*!< MCO1 configuration */
#define RCC_CFGR_MCO1 ((uint32_t)0x01C00000)
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00400000)
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00800000)
#define RCC_CFGR_MCO1_2 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO1PRE ((uint32_t)0x003C0000)
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x00040000)
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x00080000)
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x00100000)
#define RCC_CFGR_MCO1PRE_3 ((uint32_t)0x00200000)
#define RCC_CFGR_MCO2PRE ((uint32_t)0x1E000000)
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO2PRE_3 ((uint32_t)0x10000000)
#define RCC_CFGR_MCO2 ((uint32_t)0xE0000000)
#define RCC_CFGR_MCO2_0 ((uint32_t)0x20000000)
#define RCC_CFGR_MCO2_1 ((uint32_t)0x40000000)
#define RCC_CFGR_MCO2_2 ((uint32_t)0x80000000)
/******************** Bit definition for RCC_D1CFGR register ******************/
/*!< D1HPRE configuration */
#define RCC_D1CFGR_HPRE_Pos (0U)
#define RCC_D1CFGR_HPRE_Msk (0xFU << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
#define RCC_D1CFGR_HPRE_0 (0x1U << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
#define RCC_D1CFGR_HPRE_1 (0x2U << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
#define RCC_D1CFGR_HPRE_2 (0x4U << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
#define RCC_D1CFGR_HPRE_3 (0x8U << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1U << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9U << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5U << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBU << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3U << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDU << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7U << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFU << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
/*!< D1PPRE configuration */
#define RCC_D1CFGR_D1PPRE_Pos (4U)
#define RCC_D1CFGR_D1PPRE_Msk (0x7U << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
#define RCC_D1CFGR_D1PPRE_0 (0x1U << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
#define RCC_D1CFGR_D1PPRE_1 (0x2U << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
#define RCC_D1CFGR_D1PPRE_2 (0x4U << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1U << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5U << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3U << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7U << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
#define RCC_D1CFGR_D1CPRE_Pos (8U)
#define RCC_D1CFGR_D1CPRE_Msk (0xFU << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
#define RCC_D1CFGR_D1CPRE_0 (0x1U << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
#define RCC_D1CFGR_D1CPRE_1 (0x2U << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
#define RCC_D1CFGR_D1CPRE_2 (0x4U << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
#define RCC_D1CFGR_D1CPRE_3 (0x8U << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1U << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9U << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5U << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBU << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3U << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDU << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7U << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFU << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
/******************** Bit definition for RCC_D2CFGR register ******************/
/*!< D2PPRE1 configuration */
#define RCC_D2CFGR_D2PPRE1_Pos (4U)
#define RCC_D2CFGR_D2PPRE1_Msk (0x7U << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
#define RCC_D2CFGR_D2PPRE1_0 (0x1U << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
#define RCC_D2CFGR_D2PPRE1_1 (0x2U << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
#define RCC_D2CFGR_D2PPRE1_2 (0x4U << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1U << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5U << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3U << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7U << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
/*!< D2PPRE2 configuration */
#define RCC_D2CFGR_D2PPRE2_Pos (8U)
#define RCC_D2CFGR_D2PPRE2_Msk (0x7U << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
#define RCC_D2CFGR_D2PPRE2_0 (0x1U << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
#define RCC_D2CFGR_D2PPRE2_1 (0x2U << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
#define RCC_D2CFGR_D2PPRE2_2 (0x4U << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1U << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5U << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3U << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7U << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
/******************** Bit definition for RCC_D3CFGR register ******************/
/*!< D3PPRE configuration */
#define RCC_D3CFGR_D3PPRE_Pos (4U)
#define RCC_D3CFGR_D3PPRE_Msk (0x7U << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
#define RCC_D3CFGR_D3PPRE_0 (0x1U << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
#define RCC_D3CFGR_D3PPRE_1 (0x2U << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
#define RCC_D3CFGR_D3PPRE_2 (0x4U << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1U << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5U << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3U << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7U << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
/******************** Bit definition for RCC_PLLCKSELR register *************/
#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3U << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1U << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3U << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
#define RCC_PLLCKSELR_DIVM1_Pos (4U)
#define RCC_PLLCKSELR_DIVM1_Msk (0x3FU << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
#define RCC_PLLCKSELR_DIVM1_0 (0x01U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
#define RCC_PLLCKSELR_DIVM1_1 (0x02U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
#define RCC_PLLCKSELR_DIVM1_2 (0x04U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
#define RCC_PLLCKSELR_DIVM1_3 (0x08U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
#define RCC_PLLCKSELR_DIVM1_4 (0x10U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
#define RCC_PLLCKSELR_DIVM1_5 (0x20U << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
#define RCC_PLLCKSELR_DIVM2_Pos (12U)
#define RCC_PLLCKSELR_DIVM2_Msk (0x3FU << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
#define RCC_PLLCKSELR_DIVM2_0 (0x01U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
#define RCC_PLLCKSELR_DIVM2_1 (0x02U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
#define RCC_PLLCKSELR_DIVM2_2 (0x04U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
#define RCC_PLLCKSELR_DIVM2_3 (0x08U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
#define RCC_PLLCKSELR_DIVM2_4 (0x10U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
#define RCC_PLLCKSELR_DIVM2_5 (0x20U << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
#define RCC_PLLCKSELR_DIVM3_Pos (20U)
#define RCC_PLLCKSELR_DIVM3_Msk (0x3FU << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
#define RCC_PLLCKSELR_DIVM3_0 (0x01U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
#define RCC_PLLCKSELR_DIVM3_1 (0x02U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
#define RCC_PLLCKSELR_DIVM3_2 (0x04U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
#define RCC_PLLCKSELR_DIVM3_3 (0x08U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
#define RCC_PLLCKSELR_DIVM3_4 (0x10U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
#define RCC_PLLCKSELR_DIVM3_5 (0x20U << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1U << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1U << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
#define RCC_PLLCFGR_PLL1RGE_Msk (0x3U << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
#define RCC_PLLCFGR_PLL1RGE_0 (0x0U << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
#define RCC_PLLCFGR_PLL1RGE_1 (0x1U << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
#define RCC_PLLCFGR_PLL1RGE_2 (0x2U << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
#define RCC_PLLCFGR_PLL1RGE_3 (0x3U << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1U << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1U << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
#define RCC_PLLCFGR_PLL2RGE_Msk (0x3U << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
#define RCC_PLLCFGR_PLL2RGE_0 (0x0U << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
#define RCC_PLLCFGR_PLL2RGE_1 (0x1U << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLL2RGE_2 (0x2U << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLL2RGE_3 (0x3U << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1U << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1U << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
#define RCC_PLLCFGR_PLL3RGE_Msk (0x3U << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
#define RCC_PLLCFGR_PLL3RGE_0 (0x0U << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
#define RCC_PLLCFGR_PLL3RGE_1 (0x1U << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLL3RGE_2 (0x2U << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLL3RGE_3 (0x3U << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
#define RCC_PLLCFGR_DIVP1EN_Msk (0x1U << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1U << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
#define RCC_PLLCFGR_DIVR1EN_Msk (0x1U << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
#define RCC_PLLCFGR_DIVP2EN_Msk (0x1U << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1U << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
#define RCC_PLLCFGR_DIVR2EN_Msk (0x1U << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
#define RCC_PLLCFGR_DIVP3EN_Msk (0x1U << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1U << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
#define RCC_PLLCFGR_DIVR3EN_Msk (0x1U << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
/******************** Bit definition for RCC_PLL1DIVR register ***************/
#define RCC_PLL1DIVR_N1_Pos (0U)
#define RCC_PLL1DIVR_N1_Msk (0x1FFU << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
#define RCC_PLL1DIVR_P1_Pos (9U)
#define RCC_PLL1DIVR_P1_Msk (0x7FU << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
#define RCC_PLL1DIVR_Q1_Pos (16U)
#define RCC_PLL1DIVR_Q1_Msk (0x7FU << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
#define RCC_PLL1DIVR_R1_Pos (24U)
#define RCC_PLL1DIVR_R1_Msk (0x7FU << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
/******************** Bit definition for RCC_PLL1FRACR register ***************/
#define RCC_PLL1FRACR_FRACN1_Pos (3U)
#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFU << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
/******************** Bit definition for RCC_PLL2DIVR register ***************/
#define RCC_PLL2DIVR_N2_Pos (0U)
#define RCC_PLL2DIVR_N2_Msk (0x1FFU << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
#define RCC_PLL2DIVR_P2_Pos (9U)
#define RCC_PLL2DIVR_P2_Msk (0x7FU << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
#define RCC_PLL2DIVR_Q2_Pos (16U)
#define RCC_PLL2DIVR_Q2_Msk (0x7FU << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
#define RCC_PLL2DIVR_R2_Pos (24U)
#define RCC_PLL2DIVR_R2_Msk (0x7FU << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
/******************** Bit definition for RCC_PLL2FRACR register ***************/
#define RCC_PLL2FRACR_FRACN2_Pos (3U)
#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFU << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
/******************** Bit definition for RCC_PLL3DIVR register ***************/
#define RCC_PLL3DIVR_N3_Pos (0U)
#define RCC_PLL3DIVR_N3_Msk (0x1FFU << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
#define RCC_PLL3DIVR_P3_Pos (9U)
#define RCC_PLL3DIVR_P3_Msk (0x7FU << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
#define RCC_PLL3DIVR_Q3_Pos (16U)
#define RCC_PLL3DIVR_Q3_Msk (0x7FU << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
#define RCC_PLL3DIVR_R3_Pos (24U)
#define RCC_PLL3DIVR_R3_Msk (0x7FU << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
/******************** Bit definition for RCC_PLL3FRACR register ***************/
#define RCC_PLL3FRACR_FRACN3_Pos (3U)
#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFU << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
/******************** Bit definition for RCC_D1CCIPR register ***************/
#define RCC_D1CCIPR_FMCSEL_Pos (0U)
#define RCC_D1CCIPR_FMCSEL_Msk (0x3U << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
#define RCC_D1CCIPR_FMCSEL_0 (0x1U << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
#define RCC_D1CCIPR_FMCSEL_1 (0x2U << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
#define RCC_D1CCIPR_QSPISEL_Pos (4U)
#define RCC_D1CCIPR_QSPISEL_Msk (0x3U << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
#define RCC_D1CCIPR_QSPISEL_0 (0x1U << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
#define RCC_D1CCIPR_QSPISEL_1 (0x2U << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1U << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
#define RCC_D1CCIPR_CKPERSEL_Msk (0x3U << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
#define RCC_D1CCIPR_CKPERSEL_0 (0x1U << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
#define RCC_D1CCIPR_CKPERSEL_1 (0x2U << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
/******************** Bit definition for RCC_D2CCIP1R register ***************/
#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7U << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
#define RCC_D2CCIP1R_SAI1SEL_0 (0x1U << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
#define RCC_D2CCIP1R_SAI1SEL_1 (0x2U << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
#define RCC_D2CCIP1R_SAI1SEL_2 (0x4U << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7U << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
#define RCC_D2CCIP1R_SAI23SEL_0 (0x1U << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
#define RCC_D2CCIP1R_SAI23SEL_1 (0x2U << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
#define RCC_D2CCIP1R_SAI23SEL_2 (0x4U << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7U << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
#define RCC_D2CCIP1R_SPI123SEL_0 (0x1U << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
#define RCC_D2CCIP1R_SPI123SEL_1 (0x2U << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
#define RCC_D2CCIP1R_SPI123SEL_2 (0x4U << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7U << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
#define RCC_D2CCIP1R_SPI45SEL_0 (0x1U << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
#define RCC_D2CCIP1R_SPI45SEL_1 (0x2U << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
#define RCC_D2CCIP1R_SPI45SEL_2 (0x4U << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3U << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1U << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2U << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1U << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3U << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
#define RCC_D2CCIP1R_FDCANSEL_0 (0x1U << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
#define RCC_D2CCIP1R_FDCANSEL_1 (0x2U << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
#define RCC_D2CCIP1R_SWPSEL_Msk (0x1U << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
/******************** Bit definition for RCC_D2CCIP2R register ***************/
#define RCC_D2CCIP2R_USART16SEL_Pos (3U)
#define RCC_D2CCIP2R_USART16SEL_Msk (0x7U << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
#define RCC_D2CCIP2R_USART16SEL_0 (0x1U << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
#define RCC_D2CCIP2R_USART16SEL_1 (0x2U << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
#define RCC_D2CCIP2R_USART16SEL_2 (0x4U << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
#define RCC_D2CCIP2R_USART28SEL_Msk (0x7U << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
#define RCC_D2CCIP2R_USART28SEL_0 (0x1U << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
#define RCC_D2CCIP2R_USART28SEL_1 (0x2U << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
#define RCC_D2CCIP2R_USART28SEL_2 (0x4U << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
#define RCC_D2CCIP2R_RNGSEL_Msk (0x3U << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
#define RCC_D2CCIP2R_RNGSEL_0 (0x1U << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
#define RCC_D2CCIP2R_RNGSEL_1 (0x2U << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3U << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
#define RCC_D2CCIP2R_I2C123SEL_0 (0x1U << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
#define RCC_D2CCIP2R_I2C123SEL_1 (0x2U << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
#define RCC_D2CCIP2R_USBSEL_Pos (20U)
#define RCC_D2CCIP2R_USBSEL_Msk (0x3U << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
#define RCC_D2CCIP2R_USBSEL_0 (0x1U << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
#define RCC_D2CCIP2R_USBSEL_1 (0x2U << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
#define RCC_D2CCIP2R_CECSEL_Pos (22U)
#define RCC_D2CCIP2R_CECSEL_Msk (0x3U << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
#define RCC_D2CCIP2R_CECSEL_0 (0x1U << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
#define RCC_D2CCIP2R_CECSEL_1 (0x2U << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7U << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1U << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2U << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4U << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_D3CCIPR register ***************/
#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7U << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
#define RCC_D3CCIPR_LPUART1SEL_0 (0x1U << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
#define RCC_D3CCIPR_LPUART1SEL_1 (0x2U << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
#define RCC_D3CCIPR_LPUART1SEL_2 (0x4U << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
#define RCC_D3CCIPR_I2C4SEL_Msk (0x3U << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
#define RCC_D3CCIPR_I2C4SEL_0 (0x1U << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
#define RCC_D3CCIPR_I2C4SEL_1 (0x2U << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7U << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1U << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2U << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4U << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7U << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1U << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2U << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4U << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7U << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
#define RCC_D3CCIPR_SAI4ASEL_0 (0x1U << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
#define RCC_D3CCIPR_SAI4ASEL_1 (0x2U << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
#define RCC_D3CCIPR_SAI4ASEL_2 (0x4U << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7U << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
#define RCC_D3CCIPR_SAI4BSEL_0 (0x1U << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
#define RCC_D3CCIPR_SAI4BSEL_1 (0x2U << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
#define RCC_D3CCIPR_SAI4BSEL_2 (0x4U << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
#define RCC_D3CCIPR_ADCSEL_Pos (16U)
#define RCC_D3CCIPR_ADCSEL_Msk (0x3U << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
#define RCC_D3CCIPR_ADCSEL_0 (0x1U << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
#define RCC_D3CCIPR_ADCSEL_1 (0x2U << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
#define RCC_D3CCIPR_SPI6SEL_Msk (0x7U << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
#define RCC_D3CCIPR_SPI6SEL_0 (0x1U << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
#define RCC_D3CCIPR_SPI6SEL_1 (0x2U << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
#define RCC_D3CCIPR_SPI6SEL_2 (0x4U << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (2U)
#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (3U)
#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_CSIRDYIE_Pos (4U)
#define RCC_CIER_CSIRDYIE_Msk (0x1U << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (5U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
#define RCC_CIER_PLL1RDYIE_Pos (6U)
#define RCC_CIER_PLL1RDYIE_Msk (0x1U << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
#define RCC_CIER_PLL2RDYIE_Pos (7U)
#define RCC_CIER_PLL2RDYIE_Msk (0x1U << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
#define RCC_CIER_PLL3RDYIE_Pos (8U)
#define RCC_CIER_PLL3RDYIE_Msk (0x1U << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (2U)
#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (3U)
#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_CSIRDYF_Pos (4U)
#define RCC_CIFR_CSIRDYF_Msk (0x1U << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (5U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (6U)
#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_PLL2RDYF_Pos (7U)
#define RCC_CIFR_PLL2RDYF_Msk (0x1U << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
#define RCC_CIFR_PLL3RDYF_Pos (8U)
#define RCC_CIFR_PLL3RDYF_Msk (0x1U << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSECSSF_Pos (10U)
#define RCC_CIFR_HSECSSF_Msk (0x1U << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (2U)
#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (3U)
#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_CSIRDYC_Pos (4U)
#define RCC_CICR_CSIRDYC_Msk (0x1U << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
#define RCC_CICR_HSI48RDYC_Pos (5U)
#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (6U)
#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_PLL2RDYC_Pos (7U)
#define RCC_CICR_PLL2RDYC_Msk (0x1U << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
#define RCC_CICR_PLL3RDYC_Pos (8U)
#define RCC_CICR_PLL3RDYC_Msk (0x1U << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSECSSC_Pos (10U)
#define RCC_CICR_HSECSSC_Msk (0x1U << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
/******************** Bit definition for RCC_AHB3ENR register **************/
#define RCC_AHB3ENR_MDMAEN_Pos (0U)
#define RCC_AHB3ENR_MDMAEN_Msk (0x1U << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
#define RCC_AHB3ENR_DMA2DEN_Msk (0x1U << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
#define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
#define RCC_AHB3ENR_FMCEN_Pos (12U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
#define RCC_AHB3ENR_QSPIEN_Pos (14U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1U << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_ADC12EN_Pos (5U)
#define RCC_AHB1ENR_ADC12EN_Msk (0x1U << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1U << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1U << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1U << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1U << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
#define RCC_AHB1ENR_USB2OTGHSEN_Pos (27U)
#define RCC_AHB1ENR_USB2OTGHSEN_Msk (0x1U << RCC_AHB1ENR_USB2OTGHSEN_Pos) /*!< 0x08000000 */
#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGHSEN_Msk
#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos (28U)
#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_USB2OTGHSULPIEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGHSULPIEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk
#define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)
#define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */
#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk
/******************** Bit definition for RCC_AHB4ENR register ******************/
#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
#define RCC_AHB4ENR_GPIOAEN_Msk (0x1U << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
#define RCC_AHB4ENR_GPIOBEN_Msk (0x1U << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
#define RCC_AHB4ENR_GPIOCEN_Msk (0x1U << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
#define RCC_AHB4ENR_GPIODEN_Pos (3U)
#define RCC_AHB4ENR_GPIODEN_Msk (0x1U << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
#define RCC_AHB4ENR_GPIOEEN_Msk (0x1U << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
#define RCC_AHB4ENR_GPIOFEN_Msk (0x1U << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
#define RCC_AHB4ENR_GPIOGEN_Msk (0x1U << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
#define RCC_AHB4ENR_GPIOHEN_Msk (0x1U << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
#define RCC_AHB4ENR_GPIOIEN_Msk (0x1U << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
#define RCC_AHB4ENR_GPIOJEN_Msk (0x1U << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
#define RCC_AHB4ENR_GPIOKEN_Msk (0x1U << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
#define RCC_AHB4ENR_CRCEN_Pos (19U)
#define RCC_AHB4ENR_CRCEN_Msk (0x1U << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
#define RCC_AHB4ENR_BDMAEN_Pos (21U)
#define RCC_AHB4ENR_BDMAEN_Msk (0x1U << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
#define RCC_AHB4ENR_ADC3EN_Pos (24U)
#define RCC_AHB4ENR_ADC3EN_Msk (0x1U << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
#define RCC_AHB4ENR_HSEMEN_Pos (25U)
#define RCC_AHB4ENR_HSEMEN_Msk (0x1U << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1U << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
/******************** Bit definition for RCC_APB3ENR register ******************/
#define RCC_APB3ENR_LTDCEN_Pos (3U)
#define RCC_APB3ENR_LTDCEN_Msk (0x1U << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
#define RCC_APB3ENR_WWDG1EN_Pos (6U)
#define RCC_APB3ENR_WWDG1EN_Msk (0x1U << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
/******************** Bit definition for RCC_APB1LENR register ******************/
#define RCC_APB1LENR_TIM2EN_Pos (0U)
#define RCC_APB1LENR_TIM2EN_Msk (0x1U << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
#define RCC_APB1LENR_TIM3EN_Pos (1U)
#define RCC_APB1LENR_TIM3EN_Msk (0x1U << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
#define RCC_APB1LENR_TIM4EN_Pos (2U)
#define RCC_APB1LENR_TIM4EN_Msk (0x1U << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
#define RCC_APB1LENR_TIM5EN_Pos (3U)
#define RCC_APB1LENR_TIM5EN_Msk (0x1U << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
#define RCC_APB1LENR_TIM6EN_Pos (4U)
#define RCC_APB1LENR_TIM6EN_Msk (0x1U << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
#define RCC_APB1LENR_TIM7EN_Pos (5U)
#define RCC_APB1LENR_TIM7EN_Msk (0x1U << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
#define RCC_APB1LENR_TIM12EN_Pos (6U)
#define RCC_APB1LENR_TIM12EN_Msk (0x1U << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
#define RCC_APB1LENR_TIM13EN_Pos (7U)
#define RCC_APB1LENR_TIM13EN_Msk (0x1U << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
#define RCC_APB1LENR_TIM14EN_Pos (8U)
#define RCC_APB1LENR_TIM14EN_Msk (0x1U << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
#define RCC_APB1LENR_LPTIM1EN_Msk (0x1U << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
#define RCC_APB1LENR_SPI2EN_Pos (14U)
#define RCC_APB1LENR_SPI2EN_Msk (0x1U << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
#define RCC_APB1LENR_SPI3EN_Pos (15U)
#define RCC_APB1LENR_SPI3EN_Msk (0x1U << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1U << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
#define RCC_APB1LENR_USART2EN_Pos (17U)
#define RCC_APB1LENR_USART2EN_Msk (0x1U << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
#define RCC_APB1LENR_USART3EN_Pos (18U)
#define RCC_APB1LENR_USART3EN_Msk (0x1U << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
#define RCC_APB1LENR_UART4EN_Pos (19U)
#define RCC_APB1LENR_UART4EN_Msk (0x1U << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
#define RCC_APB1LENR_UART5EN_Pos (20U)
#define RCC_APB1LENR_UART5EN_Msk (0x1U << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
#define RCC_APB1LENR_I2C1EN_Pos (21U)
#define RCC_APB1LENR_I2C1EN_Msk (0x1U << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
#define RCC_APB1LENR_I2C2EN_Pos (22U)
#define RCC_APB1LENR_I2C2EN_Msk (0x1U << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
#define RCC_APB1LENR_I2C3EN_Pos (23U)
#define RCC_APB1LENR_I2C3EN_Msk (0x1U << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
#define RCC_APB1LENR_CECEN_Pos (27U)
#define RCC_APB1LENR_CECEN_Msk (0x1U << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
#define RCC_APB1LENR_DAC12EN_Pos (29U)
#define RCC_APB1LENR_DAC12EN_Msk (0x1U << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
#define RCC_APB1LENR_UART7EN_Pos (30U)
#define RCC_APB1LENR_UART7EN_Msk (0x1U << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
#define RCC_APB1LENR_UART8EN_Pos (31U)
#define RCC_APB1LENR_UART8EN_Msk (0x1U << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
/******************** Bit definition for RCC_APB1HENR register ******************/
#define RCC_APB1HENR_CRSEN_Pos (1U)
#define RCC_APB1HENR_CRSEN_Msk (0x1U << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
#define RCC_APB1HENR_SWPMIEN_Pos (2U)
#define RCC_APB1HENR_SWPMIEN_Msk (0x1U << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
#define RCC_APB1HENR_OPAMPEN_Pos (4U)
#define RCC_APB1HENR_OPAMPEN_Msk (0x1U << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
#define RCC_APB1HENR_MDIOSEN_Pos (5U)
#define RCC_APB1HENR_MDIOSEN_Msk (0x1U << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
#define RCC_APB1HENR_FDCANEN_Pos (8U)
#define RCC_APB1HENR_FDCANEN_Msk (0x1U << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
/******************** Bit definition for RCC_APB2ENR register ******************/
#define RCC_APB2ENR_TIM1EN_Pos (0U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (1U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (4U)
#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_USART6EN_Pos (5U)
#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_SPI4EN_Pos (13U)
#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_SPI5EN_Pos (20U)
#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (22U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
#define RCC_APB2ENR_SAI2EN_Pos (23U)
#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
#define RCC_APB2ENR_SAI3EN_Pos (24U)
#define RCC_APB2ENR_SAI3EN_Msk (0x1U << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
#define RCC_APB2ENR_DFSDM1EN_Pos (28U)
#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
#define RCC_APB2ENR_HRTIMEN_Pos (29U)
#define RCC_APB2ENR_HRTIMEN_Msk (0x1U << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
/******************** Bit definition for RCC_APB4ENR register ******************/
#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
#define RCC_APB4ENR_SYSCFGEN_Msk (0x1U << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
#define RCC_APB4ENR_LPUART1EN_Pos (3U)
#define RCC_APB4ENR_LPUART1EN_Msk (0x1U << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
#define RCC_APB4ENR_SPI6EN_Pos (5U)
#define RCC_APB4ENR_SPI6EN_Msk (0x1U << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
#define RCC_APB4ENR_I2C4EN_Pos (7U)
#define RCC_APB4ENR_I2C4EN_Msk (0x1U << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
#define RCC_APB4ENR_LPTIM2EN_Msk (0x1U << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
#define RCC_APB4ENR_LPTIM3EN_Msk (0x1U << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
#define RCC_APB4ENR_LPTIM4EN_Msk (0x1U << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
#define RCC_APB4ENR_LPTIM5EN_Msk (0x1U << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
#define RCC_APB4ENR_COMP12EN_Pos (14U)
#define RCC_APB4ENR_COMP12EN_Msk (0x1U << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
#define RCC_APB4ENR_VREFEN_Pos (15U)
#define RCC_APB4ENR_VREFEN_Msk (0x1U << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
#define RCC_APB4ENR_RTCAPBEN_Msk (0x1U << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
#define RCC_APB4ENR_SAI4EN_Pos (21U)
#define RCC_APB4ENR_SAI4EN_Msk (0x1U << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
/******************** Bit definition for RCC_AHB3RSTR register ***************/
#define RCC_AHB3RSTR_MDMARST_Pos (0U)
#define RCC_AHB3RSTR_MDMARST_Msk (0x1U << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1U << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1U << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
#define RCC_AHB3RSTR_FMCRST_Pos (12U)
#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
#define RCC_AHB3RSTR_QSPIRST_Pos (14U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1U << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
#define RCC_AHB3RSTR_CPURST_Pos (31U)
#define RCC_AHB3RSTR_CPURST_Msk (0x1U << RCC_AHB3RSTR_CPURST_Pos) /*!< 0x80000000 */
#define RCC_AHB3RSTR_CPURST RCC_AHB3RSTR_CPURST_Msk
/******************** Bit definition for RCC_AHB1RSTR register ***************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
#define RCC_AHB1RSTR_ADC12RST_Msk (0x1U << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1U << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1U << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
#define RCC_AHB1RSTR_USB2OTGHSRST_Pos (27U)
#define RCC_AHB1RSTR_USB2OTGHSRST_Msk (0x1U << RCC_AHB1RSTR_USB2OTGHSRST_Pos) /*!< 0x08000000 */
#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGHSRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register ***************/
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1U << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
/******************** Bit definition for RCC_AHB4RSTR register ******************/
#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
#define RCC_AHB4RSTR_GPIOARST_Msk (0x1U << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
#define RCC_AHB4RSTR_GPIODRST_Msk (0x1U << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
#define RCC_AHB4RSTR_GPIOERST_Msk (0x1U << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
#define RCC_AHB4RSTR_CRCRST_Pos (19U)
#define RCC_AHB4RSTR_CRCRST_Msk (0x1U << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
#define RCC_AHB4RSTR_BDMARST_Pos (21U)
#define RCC_AHB4RSTR_BDMARST_Msk (0x1U << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
#define RCC_AHB4RSTR_ADC3RST_Msk (0x1U << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
#define RCC_AHB4RSTR_HSEMRST_Msk (0x1U << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
/******************** Bit definition for RCC_APB3RSTR register ******************/
#define RCC_APB3RSTR_LTDCRST_Pos (3U)
#define RCC_APB3RSTR_LTDCRST_Msk (0x1U << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
/******************** Bit definition for RCC_APB1LRSTR register ******************/
#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
#define RCC_APB1LRSTR_TIM2RST_Msk (0x1U << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
#define RCC_APB1LRSTR_TIM3RST_Msk (0x1U << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
#define RCC_APB1LRSTR_TIM4RST_Msk (0x1U << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
#define RCC_APB1LRSTR_TIM5RST_Msk (0x1U << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
#define RCC_APB1LRSTR_TIM6RST_Msk (0x1U << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
#define RCC_APB1LRSTR_TIM7RST_Msk (0x1U << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
#define RCC_APB1LRSTR_TIM12RST_Msk (0x1U << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
#define RCC_APB1LRSTR_TIM13RST_Msk (0x1U << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
#define RCC_APB1LRSTR_TIM14RST_Msk (0x1U << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1U << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
#define RCC_APB1LRSTR_SPI2RST_Msk (0x1U << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
#define RCC_APB1LRSTR_SPI3RST_Msk (0x1U << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
#define RCC_APB1LRSTR_USART2RST_Pos (17U)
#define RCC_APB1LRSTR_USART2RST_Msk (0x1U << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
#define RCC_APB1LRSTR_USART3RST_Pos (18U)
#define RCC_APB1LRSTR_USART3RST_Msk (0x1U << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
#define RCC_APB1LRSTR_UART4RST_Pos (19U)
#define RCC_APB1LRSTR_UART4RST_Msk (0x1U << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
#define RCC_APB1LRSTR_UART5RST_Pos (20U)
#define RCC_APB1LRSTR_UART5RST_Msk (0x1U << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
#define RCC_APB1LRSTR_I2C1RST_Msk (0x1U << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
#define RCC_APB1LRSTR_I2C2RST_Msk (0x1U << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
#define RCC_APB1LRSTR_I2C3RST_Msk (0x1U << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
#define RCC_APB1LRSTR_CECRST_Pos (27U)
#define RCC_APB1LRSTR_CECRST_Msk (0x1U << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
#define RCC_APB1LRSTR_DAC12RST_Msk (0x1U << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
#define RCC_APB1LRSTR_UART7RST_Pos (30U)
#define RCC_APB1LRSTR_UART7RST_Msk (0x1U << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
#define RCC_APB1LRSTR_UART8RST_Pos (31U)
#define RCC_APB1LRSTR_UART8RST_Msk (0x1U << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
/******************** Bit definition for RCC_APB1HRSTR register ******************/
#define RCC_APB1HRSTR_CRSRST_Pos (1U)
#define RCC_APB1HRSTR_CRSRST_Msk (0x1U << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1U << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1U << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1U << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
#define RCC_APB1HRSTR_FDCANRST_Msk (0x1U << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
/******************** Bit definition for RCC_APB2RSTR register ******************/
#define RCC_APB2RSTR_TIM1RST_Pos (0U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (1U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (4U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_USART6RST_Pos (5U)
#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_SPI4RST_Pos (13U)
#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_SPI5RST_Pos (20U)
#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (22U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
#define RCC_APB2RSTR_SAI2RST_Pos (23U)
#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
#define RCC_APB2RSTR_SAI3RST_Pos (24U)
#define RCC_APB2RSTR_SAI3RST_Msk (0x1U << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
#define RCC_APB2RSTR_HRTIMRST_Pos (29U)
#define RCC_APB2RSTR_HRTIMRST_Msk (0x1U << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
/******************** Bit definition for RCC_APB4RSTR register ******************/
#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1U << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
#define RCC_APB4RSTR_LPUART1RST_Msk (0x1U << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
#define RCC_APB4RSTR_SPI6RST_Pos (5U)
#define RCC_APB4RSTR_SPI6RST_Msk (0x1U << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
#define RCC_APB4RSTR_I2C4RST_Pos (7U)
#define RCC_APB4RSTR_I2C4RST_Msk (0x1U << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1U << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1U << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1U << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1U << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
#define RCC_APB4RSTR_COMP12RST_Pos (14U)
#define RCC_APB4RSTR_COMP12RST_Msk (0x1U << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
#define RCC_APB4RSTR_VREFRST_Pos (15U)
#define RCC_APB4RSTR_VREFRST_Msk (0x1U << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
#define RCC_APB4RSTR_SAI4RST_Pos (21U)
#define RCC_APB4RSTR_SAI4RST_Msk (0x1U << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
/******************** Bit definition for RCC_GCR register ********************/
#define RCC_GCR_WW1RSC_Pos (0U)
#define RCC_GCR_WW1RSC_Msk (0x1U << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
/******************** Bit definition for RCC_D3AMR register ********************/
#define RCC_D3AMR_BDMAAMEN_Pos (0U)
#define RCC_D3AMR_BDMAAMEN_Msk (0x1U << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
#define RCC_D3AMR_LPUART1AMEN_Msk (0x1U << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
#define RCC_D3AMR_SPI6AMEN_Pos (5U)
#define RCC_D3AMR_SPI6AMEN_Msk (0x1U << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
#define RCC_D3AMR_I2C4AMEN_Pos (7U)
#define RCC_D3AMR_I2C4AMEN_Msk (0x1U << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1U << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1U << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1U << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1U << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
#define RCC_D3AMR_COMP12AMEN_Pos (14U)
#define RCC_D3AMR_COMP12AMEN_Msk (0x1U << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
#define RCC_D3AMR_VREFAMEN_Pos (15U)
#define RCC_D3AMR_VREFAMEN_Msk (0x1U << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
#define RCC_D3AMR_RTCAMEN_Pos (16U)
#define RCC_D3AMR_RTCAMEN_Msk (0x1U << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
#define RCC_D3AMR_CRCAMEN_Pos (19U)
#define RCC_D3AMR_CRCAMEN_Msk (0x1U << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
#define RCC_D3AMR_SAI4AMEN_Pos (21U)
#define RCC_D3AMR_SAI4AMEN_Msk (0x1U << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
#define RCC_D3AMR_ADC3AMEN_Pos (24U)
#define RCC_D3AMR_ADC3AMEN_Msk (0x1U << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1U << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
#define RCC_D3AMR_SRAM4AMEN_Msk (0x1U << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
/******************** Bit definition for RCC_AHB3LPENR register **************/
#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1U << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1U << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1U << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1U << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1U << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1U << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1U << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1U << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
/******************** Bit definition for RCC_AHB1LPENR register ***************/
#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1U << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos (27U)
#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_USB2OTGHSLPEN_Pos) /*!< 0x08000000 */
#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGHSLPEN_Msk
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos (28U)
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk
/******************** Bit definition for RCC_AHB2LPENR register ***************/
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1U << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)
#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1U << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk
#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)
#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1U << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk
#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)
#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1U << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */
#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk
/******************** Bit definition for RCC_AHB4LPENR register ******************/
#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1U << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1U << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1U << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1U << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)
#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1U << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
/******************** Bit definition for RCC_APB3LPENR register ******************/
#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1U << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1U << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
/******************** Bit definition for RCC_APB1LLPENR register ******************/
#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1U << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1U << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1U << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1U << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
#define RCC_APB1LLPENR_CECLPEN_Msk (0x1U << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1U << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1U << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1U << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
/******************** Bit definition for RCC_APB1HLPENR register ******************/
#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1U << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1U << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1U << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1U << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1U << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
/******************** Bit definition for RCC_APB2LPENR register ******************/
#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1U << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1U << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1U << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1U << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1U << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
/******************** Bit definition for RCC_APB4LPENR register ******************/
#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1U << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1U << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1U << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1U << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1U << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1U << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1U << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1U << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
#define RCC_APB4LPENR_VREFLPEN_Msk (0x1U << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1U << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
/******************** Bit definition for RCC_RSR register *******************/
#define RCC_RSR_RMVF_Pos (16U)
#define RCC_RSR_RMVF_Msk (0x1U << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
#define RCC_RSR_CPURSTF_Pos (17U)
#define RCC_RSR_CPURSTF_Msk (0x1U << RCC_RSR_CPURSTF_Pos) /*!< 0x00020000 */
#define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
#define RCC_RSR_D1RSTF_Pos (19U)
#define RCC_RSR_D1RSTF_Msk (0x1U << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
#define RCC_RSR_D2RSTF_Pos (20U)
#define RCC_RSR_D2RSTF_Msk (0x1U << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
#define RCC_RSR_BORRSTF_Pos (21U)
#define RCC_RSR_BORRSTF_Msk (0x1U << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
#define RCC_RSR_PINRSTF_Pos (22U)
#define RCC_RSR_PINRSTF_Msk (0x1U << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
#define RCC_RSR_PORRSTF_Pos (23U)
#define RCC_RSR_PORRSTF_Msk (0x1U << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
#define RCC_RSR_SFTRSTF_Pos (24U)
#define RCC_RSR_SFTRSTF_Msk (0x1U << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
#define RCC_RSR_IWDG1RSTF_Pos (26U)
#define RCC_RSR_IWDG1RSTF_Msk (0x1U << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
#define RCC_RSR_WWDG1RSTF_Pos (28U)
#define RCC_RSR_WWDG1RSTF_Msk (0x1U << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
#define RCC_RSR_LPWRRSTF_Pos (30U)
#define RCC_RSR_LPWRRSTF_Msk (0x1U << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF_Pos (17U)
#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
#define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
#define RTC_ISR_TAMP3F_Pos (15U)
#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
#define RTC_ISR_TAMP2F_Pos (14U)
#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
#define RTC_ISR_TAMP1F_Pos (13U)
#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
#define RTC_ISR_TSOVF_Pos (12U)
#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
#define RTC_ISR_TSF_Pos (11U)
#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
#define RTC_ISR_TSF RTC_ISR_TSF_Msk
#define RTC_ISR_WUTF_Pos (10U)
#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
#define RTC_ISR_ALRBF_Pos (9U)
#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
#define RTC_ISR_ALRAF_Pos (8U)
#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
#define RTC_ISR_INIT_Pos (7U)
#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ISR_INIT RTC_ISR_INIT_Msk
#define RTC_ISR_INITF_Pos (6U)
#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ISR_INITF RTC_ISR_INITF_Msk
#define RTC_ISR_RSF_Pos (5U)
#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ISR_RSF RTC_ISR_RSF_Msk
#define RTC_ISR_INITS_Pos (4U)
#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ISR_INITS RTC_ISR_INITS_Msk
#define RTC_ISR_SHPF_Pos (3U)
#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
#define RTC_ISR_WUTWF_Pos (2U)
#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
#define RTC_ISR_ALRBWF_Pos (1U)
#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
#define RTC_ISR_ALRAWF_Pos (0U)
#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_CAL register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAMPCR_TAMP3MF_Pos (24U)
#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
#define RTC_TAMPCR_TAMP3IE_Pos (22U)
#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
#define RTC_TAMPCR_TAMP2MF_Pos (21U)
#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
#define RTC_TAMPCR_TAMP2IE_Pos (19U)
#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
#define RTC_TAMPCR_TAMP1MF_Pos (18U)
#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
#define RTC_TAMPCR_TAMP1IE_Pos (16U)
#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
#define RTC_TAMPCR_TAMPFLT_Pos (11U)
#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
#define RTC_TAMPCR_TAMPTS_Pos (7U)
#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
#define RTC_TAMPCR_TAMP3_TRG_Pos (6U)
#define RTC_TAMPCR_TAMP3_TRG_Msk (0x1U << RTC_TAMPCR_TAMP3_TRG_Pos) /*!< 0x00000040 */
#define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3_TRG_Msk
#define RTC_TAMPCR_TAMP3E_Pos (5U)
#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
#define RTC_TAMPCR_TAMP2_TRG_Pos (4U)
#define RTC_TAMPCR_TAMP2_TRG_Msk (0x1U << RTC_TAMPCR_TAMP2_TRG_Pos) /*!< 0x00000010 */
#define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2_TRG_Msk
#define RTC_TAMPCR_TAMP2E_Pos (3U)
#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
#define RTC_TAMPCR_TAMPIE_Pos (2U)
#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
#define RTC_TAMPCR_TAMP1_TRG_Pos (1U)
#define RTC_TAMPCR_TAMP1_TRG_Msk (0x1U << RTC_TAMPCR_TAMP1_TRG_Pos) /*!< 0x00000002 */
#define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1_TRG_Msk
#define RTC_TAMPCR_TAMP1E_Pos (0U)
#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBSSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_OR_OUT_RMP_Pos (1U)
#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
#define RTC_OR_ALARMOUTTYPE_Pos (0U)
#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R_Pos (0U)
#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP0R RTC_BKP0R_Msk
/******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R_Pos (0U)
#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP1R RTC_BKP1R_Msk
/******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R_Pos (0U)
#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP2R RTC_BKP2R_Msk
/******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R_Pos (0U)
#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP3R RTC_BKP3R_Msk
/******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R_Pos (0U)
#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP4R RTC_BKP4R_Msk
/******************** Bits definition for RTC_BKP5R register ****************/
#define RTC_BKP5R_Pos (0U)
#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP5R RTC_BKP5R_Msk
/******************** Bits definition for RTC_BKP6R register ****************/
#define RTC_BKP6R_Pos (0U)
#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP6R RTC_BKP6R_Msk
/******************** Bits definition for RTC_BKP7R register ****************/
#define RTC_BKP7R_Pos (0U)
#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP7R RTC_BKP7R_Msk
/******************** Bits definition for RTC_BKP8R register ****************/
#define RTC_BKP8R_Pos (0U)
#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP8R RTC_BKP8R_Msk
/******************** Bits definition for RTC_BKP9R register ****************/
#define RTC_BKP9R_Pos (0U)
#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP9R RTC_BKP9R_Msk
/******************** Bits definition for RTC_BKP10R register ***************/
#define RTC_BKP10R_Pos (0U)
#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP10R RTC_BKP10R_Msk
/******************** Bits definition for RTC_BKP11R register ***************/
#define RTC_BKP11R_Pos (0U)
#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP11R RTC_BKP11R_Msk
/******************** Bits definition for RTC_BKP12R register ***************/
#define RTC_BKP12R_Pos (0U)
#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP12R RTC_BKP12R_Msk
/******************** Bits definition for RTC_BKP13R register ***************/
#define RTC_BKP13R_Pos (0U)
#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP13R RTC_BKP13R_Msk
/******************** Bits definition for RTC_BKP14R register ***************/
#define RTC_BKP14R_Pos (0U)
#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP14R RTC_BKP14R_Msk
/******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R_Pos (0U)
#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP15R RTC_BKP15R_Msk
/******************** Bits definition for RTC_BKP16R register ***************/
#define RTC_BKP16R_Pos (0U)
#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP16R RTC_BKP16R_Msk
/******************** Bits definition for RTC_BKP17R register ***************/
#define RTC_BKP17R_Pos (0U)
#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP17R RTC_BKP17R_Msk
/******************** Bits definition for RTC_BKP18R register ***************/
#define RTC_BKP18R_Pos (0U)
#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP18R RTC_BKP18R_Msk
/******************** Bits definition for RTC_BKP19R register ***************/
#define RTC_BKP19R_Pos (0U)
#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP19R RTC_BKP19R_Msk
/******************** Bits definition for RTC_BKP20R register ***************/
#define RTC_BKP20R_Pos (0U)
#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP20R RTC_BKP20R_Msk
/******************** Bits definition for RTC_BKP21R register ***************/
#define RTC_BKP21R_Pos (0U)
#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP21R RTC_BKP21R_Msk
/******************** Bits definition for RTC_BKP22R register ***************/
#define RTC_BKP22R_Pos (0U)
#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP22R RTC_BKP22R_Msk
/******************** Bits definition for RTC_BKP23R register ***************/
#define RTC_BKP23R_Pos (0U)
#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP23R RTC_BKP23R_Msk
/******************** Bits definition for RTC_BKP24R register ***************/
#define RTC_BKP24R_Pos (0U)
#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP24R RTC_BKP24R_Msk
/******************** Bits definition for RTC_BKP25R register ***************/
#define RTC_BKP25R_Pos (0U)
#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP25R RTC_BKP25R_Msk
/******************** Bits definition for RTC_BKP26R register ***************/
#define RTC_BKP26R_Pos (0U)
#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP26R RTC_BKP26R_Msk
/******************** Bits definition for RTC_BKP27R register ***************/
#define RTC_BKP27R_Pos (0U)
#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP27R RTC_BKP27R_Msk
/******************** Bits definition for RTC_BKP28R register ***************/
#define RTC_BKP28R_Pos (0U)
#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP28R RTC_BKP28R_Msk
/******************** Bits definition for RTC_BKP29R register ***************/
#define RTC_BKP29R_Pos (0U)
#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP29R RTC_BKP29R_Msk
/******************** Bits definition for RTC_BKP30R register ***************/
#define RTC_BKP30R_Pos (0U)
#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP30R RTC_BKP30R_Msk
/******************** Bits definition for RTC_BKP31R register ***************/
#define RTC_BKP31R_Pos (0U)
#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP31R RTC_BKP31R_Msk
/******************** Number of backup registers ******************************/
#define RTC_BKP_NUMBER_Pos (5U)
#define RTC_BKP_NUMBER_Msk (0x1U << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
/******************************************************************************/
/* */
/* SPDIF-RX Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SPDIF_CR register *******************/
#define SPDIFRX_CR_SPDIFEN_Pos (0U)
#define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
#define SPDIFRX_CR_RXDMAEN_Pos (2U)
#define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
#define SPDIFRX_CR_RXSTEO_Pos (3U)
#define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
#define SPDIFRX_CR_DRFMT_Pos (4U)
#define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
#define SPDIFRX_CR_PMSK_Pos (6U)
#define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
#define SPDIFRX_CR_VMSK_Pos (7U)
#define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
#define SPDIFRX_CR_CUMSK_Pos (8U)
#define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
#define SPDIFRX_CR_PTMSK_Pos (9U)
#define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
#define SPDIFRX_CR_CBDMAEN_Pos (10U)
#define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
#define SPDIFRX_CR_CHSEL_Pos (11U)
#define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
#define SPDIFRX_CR_NBTR_Pos (12U)
#define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
#define SPDIFRX_CR_WFA_Pos (14U)
#define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
#define SPDIFRX_CR_INSEL_Pos (16U)
#define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
#define SPDIFRX_CR_CKSEN_Pos (20U)
#define SPDIFRX_CR_CKSEN_Msk (0x1U << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
#define SPDIFRX_CR_CKSBKPEN_Msk (0x1U << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
/******************* Bit definition for SPDIFRX_IMR register *******************/
#define SPDIFRX_IMR_RXNEIE_Pos (0U)
#define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
#define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
#define SPDIFRX_IMR_PERRIE_Pos (2U)
#define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
#define SPDIFRX_IMR_OVRIE_Pos (3U)
#define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
#define SPDIFRX_IMR_SBLKIE_Pos (4U)
#define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
#define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
#define SPDIFRX_IMR_IFEIE_Pos (6U)
#define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
/******************* Bit definition for SPDIFRX_SR register *******************/
#define SPDIFRX_SR_RXNE_Pos (0U)
#define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
#define SPDIFRX_SR_CSRNE_Pos (1U)
#define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
#define SPDIFRX_SR_PERR_Pos (2U)
#define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
#define SPDIFRX_SR_OVR_Pos (3U)
#define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
#define SPDIFRX_SR_SBD_Pos (4U)
#define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
#define SPDIFRX_SR_SYNCD_Pos (5U)
#define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
#define SPDIFRX_SR_FERR_Pos (6U)
#define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
#define SPDIFRX_SR_SERR_Pos (7U)
#define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
#define SPDIFRX_SR_TERR_Pos (8U)
#define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
#define SPDIFRX_SR_WIDTH5_Pos (16U)
#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
/******************* Bit definition for SPDIFRX_IFCR register *******************/
#define SPDIFRX_IFCR_PERRCF_Pos (2U)
#define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
#define SPDIFRX_IFCR_OVRCF_Pos (3U)
#define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
#define SPDIFRX_IFCR_SBDCF_Pos (4U)
#define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
#define SPDIFRX_DR0_DR_Pos (0U)
#define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
#define SPDIFRX_DR0_PE_Pos (24U)
#define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
#define SPDIFRX_DR0_V_Pos (25U)
#define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
#define SPDIFRX_DR0_U_Pos (26U)
#define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
#define SPDIFRX_DR0_C_Pos (27U)
#define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR0_PT_Pos (28U)
#define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
#define SPDIFRX_DR1_DR_Pos (8U)
#define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
#define SPDIFRX_DR1_PT_Pos (4U)
#define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
#define SPDIFRX_DR1_C_Pos (3U)
#define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR1_U_Pos (2U)
#define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
#define SPDIFRX_DR1_V_Pos (1U)
#define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
#define SPDIFRX_DR1_PE_Pos (0U)
#define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
#define SPDIFRX_DR1_DRNL1_Pos (16U)
#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
#define SPDIFRX_DR1_DRNL2_Pos (0U)
#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
/******************* Bit definition for SPDIFRX_CSR register *******************/
#define SPDIFRX_CSR_USR_Pos (0U)
#define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
#define SPDIFRX_CSR_CS_Pos (16U)
#define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
#define SPDIFRX_CSR_SOB_Pos (24U)
#define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
/******************* Bit definition for SPDIFRX_DIR register *******************/
#define SPDIFRX_DIR_THI_Pos (0U)
#define SPDIFRX_DIR_THI_Msk (0x1FFFU << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO_Pos (16U)
#define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
/******************* Bit definition for SPDIFRX_VERR register *******************/
#define SPDIFRX_VERR_MINREV_Pos (0U)
#define SPDIFRX_VERR_MINREV_Msk (0xFU << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
#define SPDIFRX_VERR_MAJREV_Pos (4U)
#define SPDIFRX_VERR_MAJREV_Msk (0xFU << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
/******************* Bit definition for SPDIFRX_IDR register *******************/
#define SPDIFRX_IDR_ID_Pos (0U)
#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFU << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
/******************* Bit definition for SPDIFRX_SIDR register *******************/
#define SPDIFRX_SIDR_SID_Pos (0U)
#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFU << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
#define SAI_xCR1_NOMCK 0x00080000U /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV 0x03F00000U /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 0x01000000U /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 0x02000000U /*!<Bit 5 */
#define SAI_xCR1_OSR 0x04000000U /*!<OverSampling Ratio for master clock */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[7:0](FRame Length) */
#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
#define SAI_xFRCR_FSALL 0x00007F00U /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
#define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
/* Legacy define */
#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FBOFF[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register *********************/
#define SAI_xDR_DATA 0xFFFFFFFFU
/******************* Bit definition for SAI_PDMCR register ******************/
#define SAI_PDMCR_PDMEN 0x00000001U /*!<PDM Enable */
#define SAI_PDMCR_MICNBR 0x00000030U /*!<Number of microphones */
#define SAI_PDMCR_MICNBR_0 0x00000010U /*!<Bit 0 */
#define SAI_PDMCR_MICNBR_1 0x00000020U /*!<Bit 1 */
#define SAI_PDMCR_CKEN1 0x00000100U /*!<Clock enable of bitstream clock number 1 */
#define SAI_PDMCR_CKEN2 0x00000200U /*!<Clock enable of bitstream clock number 2 */
#define SAI_PDMCR_CKEN3 0x00000400U /*!<Clock enable of bitstream clock number 3 */
#define SAI_PDMCR_CKEN4 0x00000800U /*!<Clock enable of bitstream clock number 4 */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L 0x00000007U /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 0x00000001U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM1L_1 0x00000002U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM1L_2 0x00000004U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM1R 0x00000070U /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 0x00000010U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM1R_1 0x00000020U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM1R_2 0x00000040U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM2L 0x00000700U /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 0x00000100U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM2L_1 0x00000200U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM2L_2 0x00000400U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM2R 0x00007000U /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
#define SAI_PDMDLY_DLYM2R_0 0x00001000U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM2R_1 0x00002000U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM2R_2 0x00004000U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM3L 0x00070000U /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
#define SAI_PDMDLY_DLYM3L_0 0x00010000U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM3L_1 0x00020000U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM3L_2 0x00040000U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM3R 0x00700000U /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
#define SAI_PDMDLY_DLYM3R_0 0x00100000U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM3R_1 0x00200000U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM3R_2 0x00400000U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM4L 0x07000000U /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
#define SAI_PDMDLY_DLYM4L_0 0x01000000U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM4L_1 0x02000000U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM4L_2 0x04000000U /*!<Bit 2 */
#define SAI_PDMDLY_DLYM4R 0x70000000U /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
#define SAI_PDMDLY_DLYM4R_0 0x10000000U /*!<Bit 0 */
#define SAI_PDMDLY_DLYM4R_1 0x20000000U /*!<Bit 1 */
#define SAI_PDMDLY_DLYM4R_2 0x40000000U /*!<Bit 2 */
/******************************************************************************/
/* */
/* SDMMC Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDMMC_POWER register ******************/
#define SDMMC_POWER_PWRCTRL_Pos (0U)
#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
#define SDMMC_POWER_VSWITCH_Pos (2U)
#define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
#define SDMMC_POWER_VSWITCHEN_Pos (3U)
#define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
#define SDMMC_POWER_DIRPOL_Pos (4U)
#define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
/****************** Bit definition for SDMMC_CLKCR register ******************/
#define SDMMC_CLKCR_CLKDIV_Pos (0U)
#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
#define SDMMC_CLKCR_PWRSAV_Pos (12U)
#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
#define SDMMC_CLKCR_WIDBUS_Pos (14U)
#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
#define SDMMC_CLKCR_DDR_Pos (18U)
#define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
#define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
#define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
#define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
#define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
/******************* Bit definition for SDMMC_ARG register *******************/
#define SDMMC_ARG_CMDARG_Pos (0U)
#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
/******************* Bit definition for SDMMC_CMD register *******************/
#define SDMMC_CMD_CMDINDEX_Pos (0U)
#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
#define SDMMC_CMD_CMDTRANS_Pos (6U)
#define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
#define SDMMC_CMD_CMDSTOP_Pos (7U)
#define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
#define SDMMC_CMD_WAITRESP_Pos (8U)
#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
#define SDMMC_CMD_WAITINT_Pos (10U)
#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
#define SDMMC_CMD_WAITPEND_Pos (11U)
#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDMMC_CMD_CPSMEN_Pos (12U)
#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
#define SDMMC_CMD_DTHOLD_Pos (13U)
#define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
#define SDMMC_CMD_BOOTMODE_Pos (14U)
#define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
#define SDMMC_CMD_BOOTEN_Pos (15U)
#define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
#define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
/***************** Bit definition for SDMMC_RESPCMD register *****************/
#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
/****************** Bit definition for SDMMC_RESP0 register ******************/
#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP1 register ******************/
#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP2 register ******************/
#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP3 register ******************/
#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP4 register ******************/
#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_DTIMER register *****************/
#define SDMMC_DTIMER_DATATIME_Pos (0U)
#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
/****************** Bit definition for SDMMC_DLEN register *******************/
#define SDMMC_DLEN_DATALENGTH_Pos (0U)
#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
/****************** Bit definition for SDMMC_DCTRL register ******************/
#define SDMMC_DCTRL_DTEN_Pos (0U)
#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
#define SDMMC_DCTRL_DTDIR_Pos (1U)
#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
#define SDMMC_DCTRL_DTMODE_Pos (2U)
#define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
#define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
#define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
#define SDMMC_DCTRL_RWSTART_Pos (8U)
#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
#define SDMMC_DCTRL_RWSTOP_Pos (9U)
#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
#define SDMMC_DCTRL_RWMOD_Pos (10U)
#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
#define SDMMC_DCTRL_SDIOEN_Pos (11U)
#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
#define SDMMC_DCTRL_FIFORST_Pos (13U)
#define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
/****************** Bit definition for SDMMC_DCOUNT register *****************/
#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
/****************** Bit definition for SDMMC_STA register ********************/
#define SDMMC_STA_CCRCFAIL_Pos (0U)
#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
#define SDMMC_STA_DCRCFAIL_Pos (1U)
#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
#define SDMMC_STA_CTIMEOUT_Pos (2U)
#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
#define SDMMC_STA_DTIMEOUT_Pos (3U)
#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
#define SDMMC_STA_TXUNDERR_Pos (4U)
#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
#define SDMMC_STA_RXOVERR_Pos (5U)
#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
#define SDMMC_STA_CMDREND_Pos (6U)
#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
#define SDMMC_STA_CMDSENT_Pos (7U)
#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
#define SDMMC_STA_DATAEND_Pos (8U)
#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
#define SDMMC_STA_DHOLD_Pos (9U)
#define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
#define SDMMC_STA_DBCKEND_Pos (10U)
#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDMMC_STA_RXFIFOHF_Pos (15U)
#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDMMC_STA_TXFIFOF_Pos (16U)
#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
#define SDMMC_STA_RXFIFOF_Pos (17U)
#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
#define SDMMC_STA_TXFIFOE_Pos (18U)
#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
#define SDMMC_STA_RXFIFOE_Pos (19U)
#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
#define SDMMC_STA_BUSYD0_Pos (20U)
#define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
#define SDMMC_STA_BUSYD0END_Pos (21U)
#define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
#define SDMMC_STA_SDIOIT_Pos (22U)
#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
#define SDMMC_STA_ACKFAIL_Pos (23U)
#define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
#define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
#define SDMMC_STA_VSWEND_Pos (25U)
#define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
#define SDMMC_STA_CKSTOP_Pos (26U)
#define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
#define SDMMC_STA_IDMATE_Pos (27U)
#define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
#define SDMMC_STA_IDMABTC_Pos (28U)
#define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
/******************* Bit definition for SDMMC_ICR register *******************/
#define SDMMC_ICR_CCRCFAILC_Pos (0U)
#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
#define SDMMC_ICR_DCRCFAILC_Pos (1U)
#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
#define SDMMC_ICR_TXUNDERRC_Pos (4U)
#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
#define SDMMC_ICR_RXOVERRC_Pos (5U)
#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
#define SDMMC_ICR_CMDRENDC_Pos (6U)
#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
#define SDMMC_ICR_CMDSENTC_Pos (7U)
#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
#define SDMMC_ICR_DATAENDC_Pos (8U)
#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
#define SDMMC_ICR_DHOLDC_Pos (9U)
#define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
#define SDMMC_ICR_DBCKENDC_Pos (10U)
#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
#define SDMMC_ICR_DABORTC_Pos (11U)
#define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
#define SDMMC_ICR_SDIOITC_Pos (22U)
#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
#define SDMMC_ICR_ACKFAILC_Pos (23U)
#define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
#define SDMMC_ICR_VSWENDC_Pos (25U)
#define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
#define SDMMC_ICR_CKSTOPC_Pos (26U)
#define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
#define SDMMC_ICR_IDMATEC_Pos (27U)
#define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
#define SDMMC_ICR_IDMABTCC_Pos (28U)
#define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
/****************** Bit definition for SDMMC_MASK register *******************/
#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
#define SDMMC_MASK_RXOVERRIE_Pos (5U)
#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
#define SDMMC_MASK_CMDRENDIE_Pos (6U)
#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
#define SDMMC_MASK_CMDSENTIE_Pos (7U)
#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
#define SDMMC_MASK_DATAENDIE_Pos (8U)
#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
#define SDMMC_MASK_DHOLDIE_Pos (9U)
#define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
#define SDMMC_MASK_DBCKENDIE_Pos (10U)
#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
#define SDMMC_MASK_DABORTIE_Pos (11U)
#define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDIOTIE_Pos (22U)
#define SDMMC_MASK_SDIOTIE_Msk (0x1U << SDMMC_MASK_SDIOTIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOTIE SDMMC_MASK_SDIOTIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_ACKTIME register *****************/
#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFU << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
/****************** Bit definition for SDMMC_FIFO register *******************/
#define SDMMC_FIFO_FIFODATA_Pos (0U)
#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
/****************** Bit definition for SDMMC_IDMACTRL register ****************/
#define SDMMC_IDMA_IDMAEN_Pos (0U)
#define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
#define SDMMC_IDMA_IDMABMODE_Pos (1U)
#define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
#define SDMMC_IDMA_IDMABACT_Pos (2U)
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFU << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
/******************************************************************************/
/* */
/* Delay Block Interface (DLYB) */
/* */
/******************************************************************************/
/******************* Bit definition for DLYB_CR register ********************/
#define DLYB_CR_DEN_Pos (0U)
#define DLYB_CR_DEN_Msk (0x1U << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
#define DLYB_CR_SEN_Pos (1U)
#define DLYB_CR_SEN_Msk (0x1U << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
/******************* Bit definition for DLYB_CFGR register ********************/
#define DLYB_CFGR_SEL_Pos (0U)
#define DLYB_CFGR_SEL_Msk (0xFU << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
#define DLYB_CFGR_SEL_0 (0x1U << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
#define DLYB_CFGR_SEL_1 (0x2U << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
#define DLYB_CFGR_SEL_2 (0x3U << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
#define DLYB_CFGR_SEL_3 (0x8U << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
#define DLYB_CFGR_UNIT_Pos (8U)
#define DLYB_CFGR_UNIT_Msk (0x7FU << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
#define DLYB_CFGR_UNIT_0 (0x01U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
#define DLYB_CFGR_UNIT_1 (0x02U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
#define DLYB_CFGR_UNIT_2 (0x04U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
#define DLYB_CFGR_UNIT_3 (0x08U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
#define DLYB_CFGR_UNIT_4 (0x10U << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
#define DLYB_CFGR_UNIT_5 (0x20U << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
#define DLYB_CFGR_UNIT_6 (0x40U << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
#define DLYB_CFGR_LNG_Pos (16U)
#define DLYB_CFGR_LNG_Msk (0xFFFU << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
#define DLYB_CFGR_LNG_0 (0x001U << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
#define DLYB_CFGR_LNG_1 (0x002U << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
#define DLYB_CFGR_LNG_2 (0x004U << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
#define DLYB_CFGR_LNG_3 (0x008U << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
#define DLYB_CFGR_LNG_4 (0x010U << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
#define DLYB_CFGR_LNG_5 (0x020U << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
#define DLYB_CFGR_LNG_6 (0x040U << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
#define DLYB_CFGR_LNG_7 (0x080U << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
#define DLYB_CFGR_LNG_8 (0x100U << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
#define DLYB_CFGR_LNG_9 (0x200U << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
#define DLYB_CFGR_LNG_10 (0x400U << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
#define DLYB_CFGR_LNG_11 (0x800U << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
#define DLYB_CFGR_LNGF_Pos (31U)
#define DLYB_CFGR_LNGF_Msk (0x1U << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI/I2S) */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_SPE_Pos (0U)
#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos (8U)
#define SPI_CR1_MASRX_Msk (0x1U << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos (9U)
#define SPI_CR1_CSTART_Msk (0x1U << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
#define SPI_CR1_CSUSP_Pos (10U)
#define SPI_CR1_CSUSP_Msk (0x1U << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos (11U)
#define SPI_CR1_HDDIR_Msk (0x1U << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos (12U)
#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17 ((uint32_t)0x00002000) /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos (14U)
#define SPI_CR1_RCRCINI_Msk (0x1U << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos (15U)
#define SPI_CR1_TCRCINI_Msk (0x1U << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos (16U)
#define SPI_CR1_IOLOCK_Msk (0x1U << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_TSER_Pos (16U)
#define SPI_CR2_TSER_Msk (0xFFFFU << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
#define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
#define SPI_CR2_TSIZE_Pos (0U)
#define SPI_CR2_TSIZE_Msk (0xFFFFU << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
/******************* Bit definition for SPI_CFG1 register ********************/
#define SPI_CFG1_DSIZE_Pos (0U)
#define SPI_CFG1_DSIZE_Msk (0x1FU << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
#define SPI_CFG1_DSIZE_0 (0x01U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1 (0x02U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2 (0x04U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3 (0x08U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4 (0x10U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos (5U)
#define SPI_CFG1_FTHLV_Msk (0xFU << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0 (0x1U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1 (0x2U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2 (0x4U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3 (0x8U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos (9U)
#define SPI_CFG1_UDRCFG_Msk (0x3U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
#define SPI_CFG1_UDRCFG_0 (0x1U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
#define SPI_CFG1_UDRCFG_1 (0x2U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
#define SPI_CFG1_UDRDET_Pos (11U)
#define SPI_CFG1_UDRDET_Msk (0x3U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
#define SPI_CFG1_UDRDET_0 (0x1U << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
#define SPI_CFG1_UDRDET_1 (0x2U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
#define SPI_CFG1_RXDMAEN_Pos (14U)
#define SPI_CFG1_RXDMAEN_Msk (0x1U << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos (15U)
#define SPI_CFG1_TXDMAEN_Msk (0x1U << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos (16U)
#define SPI_CFG1_CRCSIZE_Msk (0x1FU << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
#define SPI_CFG1_CRCSIZE_0 (0x01U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1 (0x02U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2 (0x04U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3 (0x08U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4 (0x10U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos (22U)
#define SPI_CFG1_CRCEN_Msk (0x1U << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
#define SPI_CFG1_MBR_Pos (28U)
#define SPI_CFG1_MBR_Msk (0x7U << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
#define SPI_CFG1_MBR_0 (0x1U << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
#define SPI_CFG1_MBR_1 (0x2U << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
#define SPI_CFG1_MBR_2 (0x4U << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
/******************* Bit definition for SPI_CFG2 register ********************/
#define SPI_CFG2_MSSI_Pos (0U)
#define SPI_CFG2_MSSI_Msk (0xFU << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0 (0x1U << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1 (0x2U << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2 (0x4U << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3 (0x8U << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos (4U)
#define SPI_CFG2_MIDI_Msk (0xFU << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0 (0x1U << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1 (0x2U << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2 (0x4U << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3 (0x8U << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
#define SPI_CFG2_IOSWP_Pos (15U)
#define SPI_CFG2_IOSWP_Msk (0x1U << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos (17U)
#define SPI_CFG2_COMM_Msk (0x3U << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0 (0x1U << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
#define SPI_CFG2_COMM_1 (0x2U << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos (19U)
#define SPI_CFG2_SP_Msk (0x7U << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0 (0x1U << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
#define SPI_CFG2_SP_1 (0x2U << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
#define SPI_CFG2_SP_2 (0x4U << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos (22U)
#define SPI_CFG2_MASTER_Msk (0x1U << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos (23U)
#define SPI_CFG2_LSBFRST_Msk (0x1U << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos (24U)
#define SPI_CFG2_CPHA_Msk (0x1U << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos (25U)
#define SPI_CFG2_CPOL_Msk (0x1U << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos (26U)
#define SPI_CFG2_SSM_Msk (0x1U << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos (28U)
#define SPI_CFG2_SSIOP_Msk (0x1U << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos (29U)
#define SPI_CFG2_SSOE_Msk (0x1U << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos (30U)
#define SPI_CFG2_SSOM_Msk (0x1U << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos (31U)
#define SPI_CFG2_AFCNTR_Msk (0x1U << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
/******************* Bit definition for SPI_IER register ********************/
#define SPI_IER_RXPIE_Pos (0U)
#define SPI_IER_RXPIE_Msk (0x1U << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos (1U)
#define SPI_IER_TXPIE_Msk (0x1U << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos (2U)
#define SPI_IER_DXPIE_Msk (0x1U << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos (3U)
#define SPI_IER_EOTIE_Msk (0x1U << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos (4U)
#define SPI_IER_TXTFIE_Msk (0x1U << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos (5U)
#define SPI_IER_UDRIE_Msk (0x1U << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos (6U)
#define SPI_IER_OVRIE_Msk (0x1U << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
#define SPI_IER_CRCIE_Pos (7U)
#define SPI_IER_CRCIE_Msk (0x1U << SPI_IER_CRCIE_Pos) /*!< 0x00000080 */
#define SPI_IER_CRCIE SPI_IER_CRCIE_Msk /*!<CRC interrupt enable */
#define SPI_IER_TIFREIE_Pos (8U)
#define SPI_IER_TIFREIE_Msk (0x1U << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos (9U)
#define SPI_IER_MODFIE_Msk (0x1U << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
#define SPI_IER_TSERIE_Pos (10U)
#define SPI_IER_TSERIE_Msk (0x1U << SPI_IER_TSERIE_Pos) /*!< 0x00000400 */
#define SPI_IER_TSERIE SPI_IER_TSERIE_Msk /*!<TSER interrupt enable */
/******************* Bit definition for SPI_SR register ********************/
#define SPI_SR_RXP_Pos (0U)
#define SPI_SR_RXP_Msk (0x1U << SPI_SR_RXP_Pos) /*!< 0x00000001 */
#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos (1U)
#define SPI_SR_TXP_Msk (0x1U << SPI_SR_TXP_Pos) /*!< 0x00000002 */
#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos (2U)
#define SPI_SR_DXP_Msk (0x1U << SPI_SR_DXP_Pos) /*!< 0x00000004 */
#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos (3U)
#define SPI_SR_EOT_Msk (0x1U << SPI_SR_EOT_Pos) /*!< 0x00000008 */
#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos (4U)
#define SPI_SR_TXTF_Msk (0x1U << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos (5U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000020 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos (7U)
#define SPI_SR_CRCE_Msk (0x1U << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos (8U)
#define SPI_SR_TIFRE_Msk (0x1U << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos (9U)
#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000200 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
#define SPI_SR_TSERF_Pos (10U)
#define SPI_SR_TSERF_Msk (0x1U << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
#define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
#define SPI_SR_SUSP_Pos (11U)
#define SPI_SR_SUSP_Msk (0x1U << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos (12U)
#define SPI_SR_TXC_Msk (0x1U << SPI_SR_TXC_Pos) /*!< 0x00001000 */
#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos (13U)
#define SPI_SR_RXPLVL_Msk (0x3U << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0 (0x1U << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1 (0x2U << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos (15U)
#define SPI_SR_RXWNE_Msk (0x1U << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos (16U)
#define SPI_SR_CTSIZE_Msk (0xFFFFU << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
/******************* Bit definition for SPI_IFCR register ********************/
#define SPI_IFCR_EOTC_Pos (3U)
#define SPI_IFCR_EOTC_Msk (0x1U << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos (4U)
#define SPI_IFCR_TXTFC_Msk (0x1U << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos (5U)
#define SPI_IFCR_UDRC_Msk (0x1U << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos (6U)
#define SPI_IFCR_OVRC_Msk (0x1U << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos (7U)
#define SPI_IFCR_CRCEC_Msk (0x1U << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos (8U)
#define SPI_IFCR_TIFREC_Msk (0x1U << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos (9U)
#define SPI_IFCR_MODFC_Msk (0x1U << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
#define SPI_IFCR_TSERFC_Pos (10U)
#define SPI_IFCR_TSERFC_Msk (0x1U << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
#define SPI_IFCR_SUSPC_Pos (11U)
#define SPI_IFCR_SUSPC_Msk (0x1U << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
/******************* Bit definition for SPI_TXDR register ********************/
#define SPI_TXDR_TXDR_Pos (0U)
#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFU << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
/******************* Bit definition for SPI_RXDR register ********************/
#define SPI_RXDR_RXDR_Pos (0U)
#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFU << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
/******************* Bit definition for SPI_CRCPOLY register ********************/
#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
/******************* Bit definition for SPI_TXCRC register ********************/
#define SPI_TXCRC_TXCRC_Pos (0U)
#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
/******************* Bit definition for SPI_RXCRC register ********************/
#define SPI_TXCRC_RXCRC_Pos (0U)
#define SPI_TXCRC_RXCRC_Msk (0xFFFFFFFFU << SPI_TXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXCRC_RXCRC SPI_TXCRC_RXCRC_Msk /* CRCRegister for receiver */
/******************* Bit definition for SPI_UDRDR register ********************/
#define SPI_UDRDR_UDRDR_Pos (0U)
#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFU << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (0U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_I2SCFG_Pos (1U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x7U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_I2SCFG_2 (0x4U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_DATLEN_Pos (8U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_CHLEN_Pos (10U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_CKPOL_Pos (11U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
#define SPI_I2SCFGR_WSINV_Pos (12U)
#define SPI_I2SCFGR_WSINV_Msk (0x1U << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
#define SPI_I2SCFGR_FIXCH_Pos (13U)
#define SPI_I2SCFGR_FIXCH_Msk (0x1U << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00002000 */
#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
#define SPI_I2SCFGR_DATFMT_Pos (12U)
#define SPI_I2SCFGR_DATFMT_Msk (0x3U << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00003000 */
#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
#define SPI_I2SCFGR_I2SDIV_Pos (16U)
#define SPI_I2SCFGR_I2SDIV_Msk (0xFFU << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SCFGR_ODD_Pos (24U)
#define SPI_I2SCFGR_ODD_Msk (0x1U << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SCFGR_MCKOE_Pos (25U)
#define SPI_I2SCFGR_MCKOE_Msk (0x1U << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_FTHRES_0 (0x1U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
#define QUADSPI_CR_FTHRES_1 (0x2U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
#define QUADSPI_CR_FTHRES_2 (0x4U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
#define QUADSPI_CR_FTHRES_3 (0x8U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
#define QUADSPI_SR_FLEVEL_6 (0x30U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003000 */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_PMCR register ******************/
#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1U << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1U << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1U << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1U << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1U << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1U << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1U << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
#define SYSCFG_PMCR_BOOSTEN_Msk (0x1U << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYCFG_PMCR_EPIS_SEL_Pos (21U)
#define SYCFG_PMCR_EPIS_SEL_Msk (0x7U << SYCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
#define SYCFG_PMCR_EPIS_SEL SYCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
#define SYCFG_PMCR_EPIS_SEL_0 (0x1U << SYCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
#define SYCFG_PMCR_EPIS_SEL_1 (0x2U << SYCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
#define SYSCFG_PMCR_EPIS_SEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
#define SYSCFG_PMCR_PA0SO_Pos (24U)
#define SYSCFG_PMCR_PA0SO_Msk (0x1U << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
#define SYSCFG_PMCR_PA1SO_Pos (25U)
#define SYSCFG_PMCR_PA1SO_Msk (0x1U << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
#define SYSCFG_PMCR_PC2SO_Pos (26U)
#define SYSCFG_PMCR_PC2SO_Msk (0x1U << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
#define SYSCFG_PMCR_PC3SO_Pos (27U)
#define SYSCFG_PMCR_PC3SO_Msk (0x1U << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x0007) /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x0070) /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0700) /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0x7000) /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) /*!<PJ[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) /*!<PK[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) /*!<PJ[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) /*!<PK[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) /*!<PJ[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) /*!<PK[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) /*!<PJ[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) /*!<PK[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x0007) /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x0070) /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0700) /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0x7000) /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) /*!<PJ[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) /*!<PK[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) /*!<PJ[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) /*!<PK[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) /*!<PJ[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) /*!<PK[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) /*!<PJ[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) /*!<PK[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x0007) /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x0070) /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0700) /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0x7000) /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) /*!<PJ[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) /*!<PJ[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) /*!<PJ[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) /*!<PJ[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x0007) /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x0070) /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0700) /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0x7000) /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) /*!<PI[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) /*!<PJ[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0080) /*!<PI[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0090) /*!<PJ[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) /*!<PI[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) /*!<PJ[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) /*!<PI[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) /*!<PJ[15] pin */
/****************** Bit definition for SYSCFG_CCCSR register ******************/
#define SYSCFG_CCCSR_EN_Pos (0U)
#define SYSCFG_CCCSR_EN_Msk (0x1U << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
#define SYSCFG_CCCSR_CS_Pos (1U)
#define SYSCFG_CCCSR_CS_Msk (0x1U << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
#define SYSCFG_CCCSR_READY_Pos (8U)
#define SYSCFG_CCCSR_READY_Msk (0x1U << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
#define SYSCFG_CCCSR_HSLV_Pos (16U)
#define SYSCFG_CCCSR_HSLV_Msk (0x1U << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
/****************** Bit definition for SYSCFG_CCVR register *******************/
#define SYSCFG_CCVR_NCV_Pos (0U)
#define SYSCFG_CCVR_NCV_Msk (0xFU << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
#define SYSCFG_CCVR_PCV_Pos (4U)
#define SYSCFG_CCVR_PCV_Msk (0xFU << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
/****************** Bit definition for SYSCFG_CCCR register *******************/
#define SYSCFG_CCCR_NCC_Pos (0U)
#define SYSCFG_CCCR_NCC_Msk (0xFU << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
#define SYSCFG_CCCR_PCC_Pos (4U)
#define SYSCFG_CCCR_PCC_Msk (0xFU << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
/****************** Bit definition for SYSCFG_PKGR register *******************/
#define SYSCFG_PKGR_PKG_Pos (0U)
#define SYSCFG_PKGR_PKG_Msk (0xFU << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
/****************** Bit definition for SYSCFG_UR0 register *******************/
#define SYSCFG_UR0_BKS_Pos (0U)
#define SYSCFG_UR0_BKS_Msk (0x1U << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
#define SYSCFG_UR0_RDP_Pos (16U)
#define SYSCFG_UR0_RDP_Msk (0xFFU << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
/****************** Bit definition for SYSCFG_UR2 register *******************/
#define SYSCFG_UR2_BORH_Pos (0U)
#define SYSCFG_UR2_BORH_Msk (0x3U << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
#define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
#define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFU << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
#define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk /*!< Core Boot Address 0 */
/****************** Bit definition for SYSCFG_UR3 register *******************/
#define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
#define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFU << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
#define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk /*!< Core Boot Address 1 */
/****************** Bit definition for SYSCFG_UR4 register *******************/
#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1U << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
/****************** Bit definition for SYSCFG_UR5 register *******************/
#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1U << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFU << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
/****************** Bit definition for SYSCFG_UR6 register *******************/
#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFU << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFU << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
/****************** Bit definition for SYSCFG_UR7 register *******************/
#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFU << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFU << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
/****************** Bit definition for SYSCFG_UR8 register *******************/
#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1U << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1U << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
/****************** Bit definition for SYSCFG_UR9 register *******************/
#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFU << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFU << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
/****************** Bit definition for SYSCFG_UR10 register *******************/
#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFU << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFU << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
/****************** Bit definition for SYSCFG_UR11 register *******************/
#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFU << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
#define SYSCFG_UR11_IWDG1M_Pos (16U)
#define SYSCFG_UR11_IWDG1M_Msk (0x1U << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
/****************** Bit definition for SYSCFG_UR12 register *******************/
#define SYSCFG_UR12_SECURE_Pos (16U)
#define SYSCFG_UR12_SECURE_Msk (0x1U << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
/****************** Bit definition for SYSCFG_UR13 register *******************/
#define SYSCFG_UR13_SDRS_Pos (0U)
#define SYSCFG_UR13_SDRS_Msk (0x3U << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
#define SYSCFG_UR13_D1SBRST_Pos (16U)
#define SYSCFG_UR13_D1SBRST_Msk (0x1U << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
/****************** Bit definition for SYSCFG_UR14 register *******************/
#define SYSCFG_UR14_D1STPRST_Pos (0U)
#define SYSCFG_UR14_D1STPRST_Msk (0x1U << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
/****************** Bit definition for SYSCFG_UR15 register *******************/
#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1U << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
/****************** Bit definition for SYSCFG_UR16 register *******************/
#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1U << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
#define SYSCFG_UR16_PKP_Pos (16U)
#define SYSCFG_UR16_PKP_Msk (0x1U << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
/****************** Bit definition for SYSCFG_UR17 register *******************/
#define SYSCFG_UR17_IOHSLV_Pos (0U)
#define SYSCFG_UR17_IOHSLV_Msk (0x1U << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS6_Pos (17U)
#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007U << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000U << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000U << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x100U << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x7U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x1U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x2U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x4U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x7U << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR3_OC6M_0 (0x1U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x2U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x4U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x100U << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
/******************* Bit definition for TIM1_AF1 register *********************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1U << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1U << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM1_AF1_BKDFBK0E_Pos (8U)
#define TIM1_AF1_BKDFBK0E_Msk (0x1U << TIM1_AF1_BKDFBK0E_Pos) /*!< 0x00000100 */
#define TIM1_AF1_BKDFBK0E TIM1_AF1_BKDFBK0E_Msk /*!<BKDFBK0E Break input DFSDM Break 0 */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1U << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1U << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
#define TIM1_AF1_ETR_SEL_Pos (14U)
#define TIM1_AF1_ETR_SEL_Msk (0xFU << TIM1_AF1_ETR_SEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETR_SEL TIM1_AF1_ETR_SEL_Msk /*!<ETR_SEL[3:0] bits (TIM1 ETR SEL) */
#define TIM1_AF1_ETR_SEL_0 (0x1U << TIM1_AF1_ETR_SEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETR_SEL_1 (0x2U << TIM1_AF1_ETR_SEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETR_SEL_2 (0x4U << TIM1_AF1_ETR_SEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETR_SEL_3 (0x8U << TIM1_AF1_ETR_SEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1U << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1U << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
#define TIM1_AF2_BK2DFBK1E_Pos (8U)
#define TIM1_AF2_BK2DFBK1E_Msk (0x1U << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1U << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1U << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
/******************* Bit definition for TIM1_TISEL register *********************/
#define TIM1_TISEL_TI1SEL_Pos (0U)
#define TIM1_TISEL_TI1SEL_Msk (0xFU << TIM1_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM1_TISEL_TI1SEL TIM1_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM1_TISEL_TI1SEL_0 (0x1U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM1_TISEL_TI1SEL_1 (0x2U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM1_TISEL_TI1SEL_2 (0x4U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM1_TISEL_TI1SEL_3 (0x8U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM1_TISEL_TI2SEL_Pos (8U)
#define TIM1_TISEL_TI2SEL_Msk (0xFU << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM1_TISEL_TI2SEL TIM1_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM1_TISEL_TI2SEL_0 (0x1U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM1_TISEL_TI2SEL_1 (0x2U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM1_TISEL_TI2SEL_2 (0x4U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM1_TISEL_TI2SEL_3 (0x8U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM1_TISEL_TI3SEL_Pos (16U)
#define TIM1_TISEL_TI3SEL_Msk (0xFU << TIM1_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM1_TISEL_TI3SEL TIM1_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM1_TISEL_TI3SEL_0 (0x1U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM1_TISEL_TI3SEL_1 (0x2U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM1_TISEL_TI3SEL_2 (0x4U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM1_TISEL_TI3SEL_3 (0x8U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM1_TISEL_TI4SEL_Pos (24U)
#define TIM1_TISEL_TI4SEL_Msk (0xFU << TIM1_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM1_TISEL_TI4SEL TIM1_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM1_TISEL_TI4SEL_0 (0x1U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM1_TISEL_TI4SEL_1 (0x2U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM1_TISEL_TI4SEL_2 (0x4U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM1_TISEL_TI4SEL_3 (0x8U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM8_AF1 register *********************/
#define TIM8_AF1_BKINE_Pos (0U)
#define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM8_AF1_BKCMP1E_Pos (1U)
#define TIM8_AF1_BKCMP1E_Msk (0x1U << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM8_AF1_BKCMP2E_Pos (2U)
#define TIM8_AF1_BKCMP2E_Msk (0x1U << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM8_AF1_BKDFBK2E_Pos (8U)
#define TIM8_AF1_BKDFBK2E_Msk (0x1U << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
#define TIM8_AF1_BKINP_Pos (9U)
#define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM8_AF1_BKCMP1P_Pos (10U)
#define TIM8_AF1_BKCMP1P_Msk (0x1U << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM8_AF1_BKCMP2P_Pos (11U)
#define TIM8_AF1_BKCMP2P_Msk (0x1U << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
#define TIM8_AF1_ETR_SEL_Pos (14U)
#define TIM8_AF1_ETR_SEL_Msk (0xFU << TIM8_AF1_ETR_SEL_Pos) /*!< 0x0003C000 */
#define TIM8_AF1_ETR_SEL TIM8_AF1_ETR_SEL_Msk /*!<ETR_SEL[3:0] bits (TIM8 ETR SEL) */
#define TIM8_AF1_ETR_SEL_0 (0x1U << TIM8_AF1_ETR_SEL_Pos) /*!< 0x00004000 */
#define TIM8_AF1_ETR_SEL_1 (0x2U << TIM8_AF1_ETR_SEL_Pos) /*!< 0x00008000 */
#define TIM8_AF1_ETR_SEL_2 (0x4U << TIM8_AF1_ETR_SEL_Pos) /*!< 0x00010000 */
#define TIM8_AF1_ETR_SEL_3 (0x8U << TIM8_AF1_ETR_SEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM8_AF2 register *********************/
#define TIM8_AF2_BK2INE_Pos (0U)
#define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
#define TIM8_AF2_BK2CMP1E_Pos (1U)
#define TIM8_AF2_BK2CMP1E_Msk (0x1U << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
#define TIM8_AF2_BK2CMP2E_Pos (2U)
#define TIM8_AF2_BK2CMP2E_Msk (0x1U << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
#define TIM8_AF2_BK2DFBK3E_Pos (8U)
#define TIM8_AF2_BK2DFBK3E_Msk (0x1U << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
#define TIM8_AF2_BK2INP_Pos (9U)
#define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
#define TIM8_AF2_BK2CMP1P_Pos (10U)
#define TIM8_AF2_BK2CMP1P_Msk (0x1U << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
#define TIM8_AF2_BK2CMP2P_Pos (11U)
#define TIM8_AF2_BK2CMP2P_Msk (0x1U << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
/******************* Bit definition for TIM8_TISEL register *********************/
#define TIM8_TISEL_TI1SEL_Pos (0U)
#define TIM8_TISEL_TI1SEL_Msk (0xFU << TIM8_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM8_TISEL_TI1SEL TIM8_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM8 TI1 SEL)*/
#define TIM8_TISEL_TI1SEL_0 (0x1U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM8_TISEL_TI1SEL_1 (0x2U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM8_TISEL_TI1SEL_2 (0x4U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM8_TISEL_TI1SEL_3 (0x8U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM8_TISEL_TI2SEL_Pos (8U)
#define TIM8_TISEL_TI2SEL_Msk (0xFU << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM8_TISEL_TI2SEL TIM8_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM8 TI2 SEL)*/
#define TIM8_TISEL_TI2SEL_0 (0x1U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM8_TISEL_TI2SEL_1 (0x2U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM8_TISEL_TI2SEL_2 (0x4U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM8_TISEL_TI2SEL_3 (0x8U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM8_TISEL_TI3SEL_Pos (16U)
#define TIM8_TISEL_TI3SEL_Msk (0xFU << TIM8_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM8_TISEL_TI3SEL TIM8_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM8 TI3 SEL)*/
#define TIM8_TISEL_TI3SEL_0 (0x1U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM8_TISEL_TI3SEL_1 (0x2U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM8_TISEL_TI3SEL_2 (0x4U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM8_TISEL_TI3SEL_3 (0x8U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM8_TISEL_TI4SEL_Pos (24U)
#define TIM8_TISEL_TI4SEL_Msk (0xFU << TIM8_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM8_TISEL_TI4SEL TIM8_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM8 TI4 SEL)*/
#define TIM8_TISEL_TI4SEL_0 (0x1U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM8_TISEL_TI4SEL_1 (0x2U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM8_TISEL_TI4SEL_2 (0x4U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM8_TISEL_TI4SEL_3 (0x8U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM2_AF1 register *********************/
#define TIM2_AF1_ETR_SEL_Pos (14U)
#define TIM2_AF1_ETR_SEL_Msk (0xFU << TIM2_AF1_ETR_SEL_Pos) /*!< 0x0003C000 */
#define TIM2_AF1_ETR_SEL TIM2_AF1_ETR_SEL_Msk /*!<ETR_SEL[3:0] bits (TIM2 ETR SEL) */
#define TIM2_AF1_ETR_SEL_0 (0x1U << TIM2_AF1_ETR_SEL_Pos) /*!< 0x00004000 */
#define TIM2_AF1_ETR_SEL_1 (0x2U << TIM2_AF1_ETR_SEL_Pos) /*!< 0x00008000 */
#define TIM2_AF1_ETR_SEL_2 (0x4U << TIM2_AF1_ETR_SEL_Pos) /*!< 0x00010000 */
#define TIM2_AF1_ETR_SEL_3 (0x8U << TIM2_AF1_ETR_SEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM2_TISEL register *********************/
#define TIM2_TISEL_TI1SEL_Pos (0U)
#define TIM2_TISEL_TI1SEL_Msk (0xFU << TIM2_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM2_TISEL_TI1SEL TIM2_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM2_TISEL_TI1SEL_0 (0x1U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM2_TISEL_TI1SEL_1 (0x2U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM2_TISEL_TI1SEL_2 (0x4U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM2_TISEL_TI1SEL_3 (0x8U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM2_TISEL_TI2SEL_Pos (8U)
#define TIM2_TISEL_TI2SEL_Msk (0xFU << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM2_TISEL_TI2SEL TIM2_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM2 TI2 SEL)*/
#define TIM2_TISEL_TI2SEL_0 (0x1U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM2_TISEL_TI2SEL_1 (0x2U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM2_TISEL_TI2SEL_2 (0x4U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM2_TISEL_TI2SEL_3 (0x8U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM2_TISEL_TI3SEL_Pos (16U)
#define TIM2_TISEL_TI3SEL_Msk (0xFU << TIM2_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM2_TISEL_TI3SEL TIM2_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM2 TI3 SEL)*/
#define TIM2_TISEL_TI3SEL_0 (0x1U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM2_TISEL_TI3SEL_1 (0x2U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM2_TISEL_TI3SEL_2 (0x4U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM2_TISEL_TI3SEL_3 (0x8U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM2_TISEL_TI4SEL_Pos (24U)
#define TIM2_TISEL_TI4SEL_Msk (0xFU << TIM2_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM2_TISEL_TI4SEL TIM2_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM2 TI4 SEL)*/
#define TIM2_TISEL_TI4SEL_0 (0x1U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM2_TISEL_TI4SEL_1 (0x2U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM2_TISEL_TI4SEL_2 (0x4U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM2_TISEL_TI4SEL_3 (0x8U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM3_AF1 register *********************/
#define TIM3_AF1_ETR_SEL_Pos (14U)
#define TIM3_AF1_ETR_SEL_Msk (0xFU << TIM3_AF1_ETR_SEL_Pos) /*!< 0x0003C000 */
#define TIM3_AF1_ETR_SEL TIM3_AF1_ETR_SEL_Msk /*!<ETR_SEL[3:0] bits (TIM3 ETR SEL) */
#define TIM3_AF1_ETR_SEL_0 (0x1U << TIM3_AF1_ETR_SEL_Pos) /*!< 0x00004000 */
#define TIM3_AF1_ETR_SEL_1 (0x2U << TIM3_AF1_ETR_SEL_Pos) /*!< 0x00008000 */
#define TIM3_AF1_ETR_SEL_2 (0x4U << TIM3_AF1_ETR_SEL_Pos) /*!< 0x00010000 */
#define TIM3_AF1_ETR_SEL_3 (0x8U << TIM3_AF1_ETR_SEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM3_TISEL register *********************/
#define TIM3_TISEL_TI1SEL_Pos (0U)
#define TIM3_TISEL_TI1SEL_Msk (0xFU << TIM3_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM3_TISEL_TI1SEL TIM3_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
#define TIM3_TISEL_TI1SEL_0 (0x1U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM3_TISEL_TI1SEL_1 (0x2U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM3_TISEL_TI1SEL_2 (0x4U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM3_TISEL_TI1SEL_3 (0x8U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM3_TISEL_TI2SEL_Pos (8U)
#define TIM3_TISEL_TI2SEL_Msk (0xFU << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM3_TISEL_TI2SEL TIM3_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
#define TIM3_TISEL_TI2SEL_0 (0x1U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM3_TISEL_TI2SEL_1 (0x2U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM3_TISEL_TI2SEL_2 (0x4U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM3_TISEL_TI2SEL_3 (0x8U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM3_TISEL_TI3SEL_Pos (16U)
#define TIM3_TISEL_TI3SEL_Msk (0xFU << TIM3_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM3_TISEL_TI3SEL TIM3_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
#define TIM3_TISEL_TI3SEL_0 (0x1U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM3_TISEL_TI3SEL_1 (0x2U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM3_TISEL_TI3SEL_2 (0x4U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM3_TISEL_TI3SEL_3 (0x8U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM3_TISEL_TI4SEL_Pos (24U)
#define TIM3_TISEL_TI4SEL_Msk (0xFU << TIM3_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM3_TISEL_TI4SEL TIM3_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
#define TIM3_TISEL_TI4SEL_0 (0x1U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM3_TISEL_TI4SEL_1 (0x2U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM3_TISEL_TI4SEL_2 (0x4U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM3_TISEL_TI4SEL_3 (0x8U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM5_AF1 register *********************/
#define TIM5_AF1_ETR_SEL_Pos (14U)
#define TIM5_AF1_ETR_SEL_Msk (0xFU << TIM5_AF1_ETR_SEL_Pos) /*!< 0x0003C000 */
#define TIM5_AF1_ETR_SEL TIM5_AF1_ETR_SEL_Msk /*!<ETR_SEL[3:0] bits (TIM5 ETR SEL) */
#define TIM5_AF1_ETR_SEL_0 (0x1U << TIM5_AF1_ETR_SEL_Pos) /*!< 0x00004000 */
#define TIM5_AF1_ETR_SEL_1 (0x2U << TIM5_AF1_ETR_SEL_Pos) /*!< 0x00008000 */
#define TIM5_AF1_ETR_SEL_2 (0x4U << TIM5_AF1_ETR_SEL_Pos) /*!< 0x00010000 */
#define TIM5_AF1_ETR_SEL_3 (0x8U << TIM5_AF1_ETR_SEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM5_TISEL register *********************/
#define TIM5_TISEL_TI1SEL_Pos (0U)
#define TIM5_TISEL_TI1SEL_Msk (0xFU << TIM5_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM5_TISEL_TI1SEL TIM5_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
#define TIM5_TISEL_TI1SEL_0 (0x1U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM5_TISEL_TI1SEL_1 (0x2U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM5_TISEL_TI1SEL_2 (0x4U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM5_TISEL_TI1SEL_3 (0x8U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM5_TISEL_TI2SEL_Pos (8U)
#define TIM5_TISEL_TI2SEL_Msk (0xFU << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM5_TISEL_TI2SEL TIM5_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
#define TIM5_TISEL_TI2SEL_0 (0x1U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM5_TISEL_TI2SEL_1 (0x2U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM5_TISEL_TI2SEL_2 (0x4U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM5_TISEL_TI2SEL_3 (0x8U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM5_TISEL_TI3SEL_Pos (16U)
#define TIM5_TISEL_TI3SEL_Msk (0xFU << TIM5_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM5_TISEL_TI3SEL TIM5_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
#define TIM5_TISEL_TI3SEL_0 (0x1U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM5_TISEL_TI3SEL_1 (0x2U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM5_TISEL_TI3SEL_2 (0x4U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM5_TISEL_TI3SEL_3 (0x8U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM5_TISEL_TI4SEL_Pos (24U)
#define TIM5_TISEL_TI4SEL_Msk (0xFU << TIM5_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM5_TISEL_TI4SEL TIM5_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
#define TIM5_TISEL_TI4SEL_0 (0x1U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM5_TISEL_TI4SEL_1 (0x2U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM5_TISEL_TI4SEL_2 (0x4U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM5_TISEL_TI4SEL_3 (0x8U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM15_AF1 register *********************/
#define TIM15_AF1_BKINE_Pos (0U)
#define TIM15_AF1_BKINE_Msk (0x1U << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM15_AF1_BKCMP1E_Pos (1U)
#define TIM15_AF1_BKCMP1E_Msk (0x1U << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM15_AF1_BKCMP2E_Pos (2U)
#define TIM15_AF1_BKCMP2E_Msk (0x1U << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM15_AF1_BKDF1BK2E_Pos (8U)
#define TIM15_AF1_BKDF1BK2E_Msk (0x1U << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
#define TIM15_AF1_BKINP_Pos (9U)
#define TIM15_AF1_BKINP_Msk (0x1U << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM15_AF1_BKCMP1P_Pos (10U)
#define TIM15_AF1_BKCMP1P_Msk (0x1U << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM15_AF1_BKCMP2P_Pos (11U)
#define TIM15_AF1_BKCMP2P_Msk (0x1U << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
/******************* Bit definition for TIM15_TISEL register *********************/
#define TIM15_TISEL_TI1SEL_Pos (0U)
#define TIM15_TISEL_TI1SEL_Msk (0xFU << TIM15_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM15_TISEL_TI1SEL TIM15_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM15 TI1 SEL)*/
#define TIM15_TISEL_TI1SEL_0 (0x1U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM15_TISEL_TI1SEL_1 (0x2U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM15_TISEL_TI1SEL_2 (0x4U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM15_TISEL_TI1SEL_3 (0x8U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM15_TISEL_TI2SEL_Pos (8U)
#define TIM15_TISEL_TI2SEL_Msk (0xFU << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM15_TISEL_TI2SEL TIM15_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
#define TIM15_TISEL_TI2SEL_0 (0x1U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM15_TISEL_TI2SEL_1 (0x2U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM15_TISEL_TI2SEL_2 (0x4U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM15_TISEL_TI2SEL_3 (0x8U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
/******************* Bit definition for TIM16_ register *********************/
#define TIM16_AF1_BKINE_Pos (0U)
#define TIM16_AF1_BKINE_Msk (0x1U << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM16_AF1_BKCMP1E_Pos (1U)
#define TIM16_AF1_BKCMP1E_Msk (0x1U << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM16_AF1_BKCMP2E_Pos (2U)
#define TIM16_AF1_BKCMP2E_Msk (0x1U << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM16_AF1_BKDF1BK2E_Pos (8U)
#define TIM16_AF1_BKDF1BK2E_Msk (0x1U << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
#define TIM16_AF1_BKINP_Pos (9U)
#define TIM16_AF1_BKINP_Msk (0x1U << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM16_AF1_BKCMP1P_Pos (10U)
#define TIM16_AF1_BKCMP1P_Msk (0x1U << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM16_AF1_BKCMP2P_Pos (11U)
#define TIM16_AF1_BKCMP2P_Msk (0x1U << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
/******************* Bit definition for TIM16_TISEL register *********************/
#define TIM16_TISEL_TI1SEL_Pos (0U)
#define TIM16_TISEL_TI1SEL_Msk (0xFU << TIM16_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM16_TISEL_TI1SEL TIM16_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM16 TI1 SEL) */
#define TIM16_TISEL_TI1SEL_0 (0x1U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM16_TISEL_TI1SEL_1 (0x2U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM16_TISEL_TI1SEL_2 (0x4U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM16_TISEL_TI1SEL_3 (0x8U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
/******************* Bit definition for TIM17_AF1 register *********************/
#define TIM17_AF1_BKINE_Pos (0U)
#define TIM17_AF1_BKINE_Msk (0x1U << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM17_AF1_BKCMP1E_Pos (1U)
#define TIM17_AF1_BKCMP1E_Msk (0x1U << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM17_AF1_BKCMP2E_Pos (2U)
#define TIM17_AF1_BKCMP2E_Msk (0x1U << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM17_AF1_BKDF1BK2E_Pos (8U)
#define TIM17_AF1_BKDF1BK2E_Msk (0x1U << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
#define TIM17_AF1_BKINP_Pos (9U)
#define TIM17_AF1_BKINP_Msk (0x1U << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM17_AF1_BKCMP1P_Pos (10U)
#define TIM17_AF1_BKCMP1P_Msk (0x1U << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM17_AF1_BKCMP2P_Pos (11U)
#define TIM17_AF1_BKCMP2P_Msk (0x1U << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
/******************* Bit definition for TIM17_TISEL register *********************/
#define TIM17_TISEL_TI1SEL_Pos (0U)
#define TIM17_TISEL_TI1SEL_Msk (0xFU << TIM17_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM17_TISEL_TI1SEL TIM17_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM17 TI1 SEL) */
#define TIM17_TISEL_TI1SEL_0 (0x1U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM17_TISEL_TI1SEL_1 (0x2U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM17_TISEL_TI1SEL_2 (0x4U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM17_TISEL_TI1SEL_3 (0x8U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Low Power Timer (LPTTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x40001U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_CFGR2_CFGR2_Pos (0U)
#define LPTIM_CFGR2_CFGR2_Msk (0xFFU << LPTIM_CFGR2_CFGR2_Pos) /*!< 0x000000FF */
#define LPTIM_CFGR2_CFGR2 LPTIM_CFGR2_CFGR2_Msk /*!< LPTIMER_ CFGR2[7:0] bits (Remap selection) */
#define LPTIM_CFGR2_IN1_SEL0_Pos (0U)
#define LPTIM_CFGR2_IN1_SEL0_Msk (0x1U << LPTIM_CFGR2_IN1_SEL0_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1_SEL0 LPTIM_CFGR2_IN1_SEL0_Msk /*!< Bit 0 */
#define LPTIM_CFGR2_IN1_SEL1_Pos (1U)
#define LPTIM_CFGR2_IN1_SEL1_Msk (0x1U << LPTIM_CFGR2_IN1_SEL1_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR2_IN1_SEL1 LPTIM_CFGR2_IN1_SEL1_Msk /*!< Bit 1 */
#define LPTIM_CFGR2_IN2_SEL0_Pos (4U)
#define LPTIM_CFGR2_IN2_SEL0_Msk (0x1U << LPTIM_CFGR2_IN2_SEL0_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2_SEL0 LPTIM_CFGR2_IN2_SEL0_Msk /*!< Bit 4 */
#define LPTIM_CFGR2_IN2_SEL1_Pos (5U)
#define LPTIM_CFGR2_IN2_SEL1_Msk (0x1U << LPTIM_CFGR2_IN2_SEL1_Pos) /*!< 0x00000020 */
#define LPTIM_CFGR2_IN2_SEL1 LPTIM_CFGR2_IN2_SEL1_Msk /*!< Bit 5 */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/******************* Bit definition for COMP_SR register ********************/
#define COMP_SR_C1VAL_Pos (0U)
#define COMP_SR_C1VAL_Msk (0x1U << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
#define COMP_SR_C2VAL_Pos (1U)
#define COMP_SR_C2VAL_Msk (0x1U << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
#define COMP_SR_C1IF_Pos (16U)
#define COMP_SR_C1IF_Msk (0x1U << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
#define COMP_SR_C1IF COMP_SR_C1IF_Msk
#define COMP_SR_C2IF_Pos (17U)
#define COMP_SR_C2IF_Msk (0x1U << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
#define COMP_SR_C2IF COMP_SR_C2IF_Msk
/******************* Bit definition for COMP_ICFR register ********************/
#define COMP_ICFR_C1IF_Pos (16U)
#define COMP_ICFR_C1IF_Msk (0x1U << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
#define COMP_ICFR_C2IF_Pos (17U)
#define COMP_ICFR_C2IF_Msk (0x1U << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
/******************* Bit definition for COMP_OR register ********************/
#define COMP_OR_AFOPA6_Pos (0U)
#define COMP_OR_AFOPA6_Msk (0x1U << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
#define COMP_OR_AFOPA8_Pos (1U)
#define COMP_OR_AFOPA8_Msk (0x1U << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
#define COMP_OR_AFOPB12_Pos (2U)
#define COMP_OR_AFOPB12_Msk (0x1U << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
#define COMP_OR_AFOPE6_Pos (3U)
#define COMP_OR_AFOPE6_Msk (0x1U << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
#define COMP_OR_AFOPE15_Pos (4U)
#define COMP_OR_AFOPE15_Msk (0x1U << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
#define COMP_OR_AFOPG2_Pos (5U)
#define COMP_OR_AFOPG2_Msk (0x1U << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
#define COMP_OR_AFOPG3_Pos (6U)
#define COMP_OR_AFOPG3_Msk (0x1U << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
#define COMP_OR_AFOPG4_Pos (7U)
#define COMP_OR_AFOPG4_Msk (0x1U << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
#define COMP_OR_AFOPI1_Pos (8U)
#define COMP_OR_AFOPI1_Msk (0x1U << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
#define COMP_OR_AFOPI4_Pos (9U)
#define COMP_OR_AFOPI4_Msk (0x1U << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
#define COMP_OR_AFOPK2_Pos (10U)
#define COMP_OR_AFOPK2_Msk (0x1U << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
/*!< ****************** Bit definition for COMP_CFGRx register ********************/
#define COMP_CFGRx_EN_Pos (0U)
#define COMP_CFGRx_EN_Msk (0x1U << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
#define COMP_CFGRx_BRGEN_Pos (1U)
#define COMP_CFGRx_BRGEN_Msk (0x1U << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
#define COMP_CFGRx_SCALEN_Pos (2U)
#define COMP_CFGRx_SCALEN_Msk (0x1U << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
#define COMP_CFGRx_POLARITY_Pos (3U)
#define COMP_CFGRx_POLARITY_Msk (0x1U << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
#define COMP_CFGRx_WINMODE_Pos (4U)
#define COMP_CFGRx_WINMODE_Msk (0x1U << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
#define COMP_CFGRx_ITEN_Pos (6U)
#define COMP_CFGRx_ITEN_Msk (0x1U << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
#define COMP_CFGRx_HYST_Pos (8U)
#define COMP_CFGRx_HYST_Msk (0x3U << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
#define COMP_CFGRx_HYST_0 (0x1U << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
#define COMP_CFGRx_HYST_1 (0x2U << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
#define COMP_CFGRx_PWRMODE_Pos (12U)
#define COMP_CFGRx_PWRMODE_Msk (0x3U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
#define COMP_CFGRx_PWRMODE_0 (0x1U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
#define COMP_CFGRx_PWRMODE_1 (0x2U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
#define COMP_CFGRx_INMSEL_Pos (16U)
#define COMP_CFGRx_INMSEL_Msk (0x7U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
#define COMP_CFGRx_INMSEL_0 (0x1U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
#define COMP_CFGRx_INMSEL_1 (0x2U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
#define COMP_CFGRx_INMSEL_2 (0x4U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
#define COMP_CFGRx_INPSEL_Pos (20U)
#define COMP_CFGRx_INPSEL_Msk (0x1U << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
#define COMP_CFGRx_BLANKING_Pos (24U)
#define COMP_CFGRx_BLANKING_Msk (0xFU << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
#define COMP_CFGRx_BLANKING_0 (0x1U << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
#define COMP_CFGRx_BLANKING_1 (0x2U << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
#define COMP_CFGRx_BLANKING_2 (0x4U << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
#define COMP_CFGRx_LOCK_Pos (31U)
#define COMP_CFGRx_LOCK_Msk (0x1U << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION_Pos (0U)
#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA_Pos (4U)
#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NCF_Pos (2U)
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGT_Pos (7U)
#define USART_ICR_TCBGT_Msk (0x1U << USART_ICR_TCBGT_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGT USART_ICR_TCBGT_Msk /*!< Transmission complete before guard time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ******************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
/******************************************************************************/
/* */
/* Single Wire Protocol Master Interface (SWPMI) */
/* */
/******************************************************************************/
/******************* Bit definition for SWPMI_CR register ********************/
#define SWPMI_CR_RXDMA ((uint16_t)0x0001) /*!<Reception DMA enable */
#define SWPMI_CR_TXDMA ((uint16_t)0x0002) /*!<Transmission DMA enable */
#define SWPMI_CR_RXMODE ((uint16_t)0x0004) /*!<Reception buffering mode */
#define SWPMI_CR_TXMODE ((uint16_t)0x0008) /*!<Transmission buffering mode */
#define SWPMI_CR_LPBK ((uint16_t)0x0010) /*!<Loopback mode enable */
#define SWPMI_CR_SWPACT ((uint16_t)0x0020) /*!<Single wire protocol master interface activate */
#define SWPMI_CR_DEACT ((uint16_t)0x0400) /*!<Single wire protocol master interface deactivate */
#define SWPMI_CR_SWPEN ((uint16_t)0x0800) /*!<Single wire protocol master transceiver enable */
/******************* Bit definition for SWPMI_BRR register ********************/
#define SWPMI_BRR_BR ((uint16_t)0x003F) /*!<BR[7:0] bits (Bitrate prescaler) */
/******************* Bit definition for SWPMI_ISR register ********************/
#define SWPMI_ISR_RXBFF ((uint16_t)0x0001) /*!<Receive buffer full flag */
#define SWPMI_ISR_TXBEF ((uint16_t)0x0002) /*!<Transmit buffer empty flag */
#define SWPMI_ISR_RXBERF ((uint16_t)0x0004) /*!<Receive CRC error flag */
#define SWPMI_ISR_RXOVRF ((uint16_t)0x0008) /*!<Receive overrun error flag */
#define SWPMI_ISR_TXUNRF ((uint16_t)0x0010) /*!<Transmit underrun error flag */
#define SWPMI_ISR_RXNE ((uint16_t)0x0020) /*!<Receive data register not empty */
#define SWPMI_ISR_TXE ((uint16_t)0x0040) /*!<Transmit data register empty */
#define SWPMI_ISR_TCF ((uint16_t)0x0080) /*!<Transfer complete flag */
#define SWPMI_ISR_SRF ((uint16_t)0x0100) /*!<Slave resume flag */
#define SWPMI_ISR_SUSP ((uint16_t)0x0200) /*!<SUSPEND flag */
#define SWPMI_ISR_DEACTF ((uint16_t)0x0400) /*!<DEACTIVATED flag */
#define SWPMI_ISR_RDYF ((uint16_t)0x0800) /*!<Transceiver ready flag */
/******************* Bit definition for SWPMI_ICR register ********************/
#define SWPMI_ICR_CRXBFF ((uint16_t)0x0001) /*!<Clear receive buffer full flag */
#define SWPMI_ICR_CTXBEF ((uint16_t)0x0002) /*!<Clear transmit buffer empty flag */
#define SWPMI_ICR_CRXBERF ((uint16_t)0x0004) /*!<Clear receive CRC error flag */
#define SWPMI_ICR_CRXOVRF ((uint16_t)0x0008) /*!<Clear receive overrun error flag */
#define SWPMI_ICR_CTXUNRF ((uint16_t)0x0010) /*!<Clear transmit underrun error flag */
#define SWPMI_ICR_CTCF ((uint16_t)0x0080) /*!<Clear transfer complete flag */
#define SWPMI_ICR_CSRF ((uint16_t)0x0100) /*!<Clear slave resume flag */
#define SWPMI_ICR_CRDYF ((uint16_t)0x0800) /*!<Clear transceiver ready flag */
/******************* Bit definition for SWPMI_IER register ********************/
#define SWPMI_IER_RXBFIE ((uint16_t)0x0001) /*!<Receive buffer full interrupt enable */
#define SWPMI_IER_TXBEIE ((uint16_t)0x0002) /*!<Transmit buffer empty interrupt enable */
#define SWPMI_IER_RXBERIE ((uint16_t)0x0004) /*!<Receive CRC error interrupt enable */
#define SWPMI_IER_RXOVRIE ((uint16_t)0x0008) /*!<Receive overrun error interrupt enable */
#define SWPMI_IER_TXUNRIE ((uint16_t)0x0010) /*!<Transmit underrun error interrupt enable */
#define SWPMI_IER_RIE ((uint16_t)0x0020) /*!<Receive interrupt enable */
#define SWPMI_IER_TIE ((uint16_t)0x0040) /*!<Transmit interrupt enable */
#define SWPMI_IER_TCIE ((uint16_t)0x0080) /*!<Transmit complete interrupt enable */
#define SWPMI_IER_SRIE ((uint16_t)0x0100) /*!<Slave resume interrupt enable */
#define SWPMI_IER_RDYIE ((uint16_t)0x0800) /*!<Transceiver ready interrupt enable */
/******************* Bit definition for SWPMI_RFL register ********************/
#define SWPMI_RFL_RFL ((uint16_t)0x001F) /*!<RFL[4:0] bits (Receive Frame length) */
#define SWPMI_RFL_RFL_0_1 ((uint16_t)0x0003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
/******************* Bit definition for SWPMI_TDR register ********************/
#define SWPMI_TDR_TD_Pos (0U)
#define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
#define SWPMI_OR_TBYP ((uint16_t)0x0001) /*!<SWP Transceiver Bypass */
#define SWPMI_OR_CLASS ((uint16_t)0x0002) /*!<SWP CLASS selection */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
#define WWDG_CFR_WDGTB ((uint16_t)0x3800) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0800) /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint16_t)0x1000) /*!<Bit 1 */
#define WWDG_CFR_WDGTB2 ((uint16_t)0x2000)
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
/* DBG */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1U << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
#define DBGMCU_CR_DBG_STOPD1_Msk (0x1U << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1U << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
#define DBGMCU_CR_DBG_STOPD3_Msk (0x1U << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1U << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1U << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1U << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1U << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1U << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
/******************** Bit definition for APB3FZ1 register ************/
#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1U << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
/******************** Bit definition for APB1LFZ1 register ************/
#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1U << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
/******************** Bit definition for APB1HFZ1 register ************/
#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1U << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
/******************** Bit definition for APB2FZ1 register ************/
#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1U << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1U << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1U << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1U << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1U << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1U << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
/******************** Bit definition for APB4FZ1 register ************/
#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1U << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1U << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1U << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1U << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1U << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1U << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1U << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
/******************************************************************************/
/* */
/* High Resolution Timer (HRTIM) */
/* */
/******************************************************************************/
/******************** Master Timer control register ***************************/
#define HRTIM_MCR_CK_PSC_Pos (0U)
#define HRTIM_MCR_CK_PSC_Msk (0x7U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
#define HRTIM_MCR_CK_PSC_0 (0x1U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
#define HRTIM_MCR_CK_PSC_1 (0x2U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
#define HRTIM_MCR_CK_PSC_2 (0x4U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
#define HRTIM_MCR_CONT_Pos (3U)
#define HRTIM_MCR_CONT_Msk (0x1U << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
#define HRTIM_MCR_RETRIG_Pos (4U)
#define HRTIM_MCR_RETRIG_Msk (0x1U << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
#define HRTIM_MCR_HALF_Pos (5U)
#define HRTIM_MCR_HALF_Msk (0x1U << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
#define HRTIM_MCR_SYNC_IN_Pos (8U)
#define HRTIM_MCR_SYNC_IN_Msk (0x3U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
#define HRTIM_MCR_SYNC_IN_0 (0x1U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
#define HRTIM_MCR_SYNC_IN_1 (0x2U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
#define HRTIM_MCR_SYNCRSTM_Pos (10U)
#define HRTIM_MCR_SYNCRSTM_Msk (0x1U << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
#define HRTIM_MCR_SYNCSTRTM_Msk (0x1U << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
#define HRTIM_MCR_SYNC_OUT_Pos (12U)
#define HRTIM_MCR_SYNC_OUT_Msk (0x3U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
#define HRTIM_MCR_SYNC_OUT_0 (0x1U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
#define HRTIM_MCR_SYNC_OUT_1 (0x2U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
#define HRTIM_MCR_SYNC_SRC_Pos (14U)
#define HRTIM_MCR_SYNC_SRC_Msk (0x3U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
#define HRTIM_MCR_SYNC_SRC_0 (0x1U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
#define HRTIM_MCR_SYNC_SRC_1 (0x2U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
#define HRTIM_MCR_MCEN_Pos (16U)
#define HRTIM_MCR_MCEN_Msk (0x1U << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
#define HRTIM_MCR_TACEN_Pos (17U)
#define HRTIM_MCR_TACEN_Msk (0x1U << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
#define HRTIM_MCR_TBCEN_Pos (18U)
#define HRTIM_MCR_TBCEN_Msk (0x1U << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
#define HRTIM_MCR_TCCEN_Pos (19U)
#define HRTIM_MCR_TCCEN_Msk (0x1U << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
#define HRTIM_MCR_TDCEN_Pos (20U)
#define HRTIM_MCR_TDCEN_Msk (0x1U << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
#define HRTIM_MCR_TECEN_Pos (21U)
#define HRTIM_MCR_TECEN_Msk (0x1U << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
#define HRTIM_MCR_DACSYNC_Pos (25U)
#define HRTIM_MCR_DACSYNC_Msk (0x3U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
#define HRTIM_MCR_DACSYNC_0 (0x1U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
#define HRTIM_MCR_DACSYNC_1 (0x2U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
#define HRTIM_MCR_PREEN_Pos (27U)
#define HRTIM_MCR_PREEN_Msk (0x1U << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
#define HRTIM_MCR_MREPU_Pos (29U)
#define HRTIM_MCR_MREPU_Msk (0x1U << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
#define HRTIM_MCR_BRSTDMA_Pos (30U)
#define HRTIM_MCR_BRSTDMA_Msk (0x3U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
#define HRTIM_MCR_BRSTDMA_0 (0x1U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
#define HRTIM_MCR_BRSTDMA_1 (0x2U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
/******************** Master Timer Interrupt status register ******************/
#define HRTIM_MISR_MCMP1_Pos (0U)
#define HRTIM_MISR_MCMP1_Msk (0x1U << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
#define HRTIM_MISR_MCMP2_Pos (1U)
#define HRTIM_MISR_MCMP2_Msk (0x1U << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
#define HRTIM_MISR_MCMP3_Pos (2U)
#define HRTIM_MISR_MCMP3_Msk (0x1U << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
#define HRTIM_MISR_MCMP4_Pos (3U)
#define HRTIM_MISR_MCMP4_Msk (0x1U << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
#define HRTIM_MISR_MREP_Pos (4U)
#define HRTIM_MISR_MREP_Msk (0x1U << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
#define HRTIM_MISR_SYNC_Pos (5U)
#define HRTIM_MISR_SYNC_Msk (0x1U << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
#define HRTIM_MISR_MUPD_Pos (6U)
#define HRTIM_MISR_MUPD_Msk (0x1U << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
/******************** Master Timer Interrupt clear register *******************/
#define HRTIM_MICR_MCMP1_Pos (0U)
#define HRTIM_MICR_MCMP1_Msk (0x1U << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
#define HRTIM_MICR_MCMP2_Pos (1U)
#define HRTIM_MICR_MCMP2_Msk (0x1U << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
#define HRTIM_MICR_MCMP3_Pos (2U)
#define HRTIM_MICR_MCMP3_Msk (0x1U << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
#define HRTIM_MICR_MCMP4_Pos (3U)
#define HRTIM_MICR_MCMP4_Msk (0x1U << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
#define HRTIM_MICR_MREP_Pos (4U)
#define HRTIM_MICR_MREP_Msk (0x1U << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
#define HRTIM_MICR_SYNC_Pos (5U)
#define HRTIM_MICR_SYNC_Msk (0x1U << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
#define HRTIM_MICR_MUPD_Pos (6U)
#define HRTIM_MICR_MUPD_Msk (0x1U << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
/******************** Master Timer DMA/Interrupt enable register **************/
#define HRTIM_MDIER_MCMP1IE_Pos (0U)
#define HRTIM_MDIER_MCMP1IE_Msk (0x1U << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
#define HRTIM_MDIER_MCMP2IE_Pos (1U)
#define HRTIM_MDIER_MCMP2IE_Msk (0x1U << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
#define HRTIM_MDIER_MCMP3IE_Pos (2U)
#define HRTIM_MDIER_MCMP3IE_Msk (0x1U << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
#define HRTIM_MDIER_MCMP4IE_Pos (3U)
#define HRTIM_MDIER_MCMP4IE_Msk (0x1U << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
#define HRTIM_MDIER_MREPIE_Pos (4U)
#define HRTIM_MDIER_MREPIE_Msk (0x1U << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
#define HRTIM_MDIER_SYNCIE_Pos (5U)
#define HRTIM_MDIER_SYNCIE_Msk (0x1U << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
#define HRTIM_MDIER_MUPDIE_Pos (6U)
#define HRTIM_MDIER_MUPDIE_Msk (0x1U << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
#define HRTIM_MDIER_MCMP1DE_Pos (16U)
#define HRTIM_MDIER_MCMP1DE_Msk (0x1U << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
#define HRTIM_MDIER_MCMP2DE_Pos (17U)
#define HRTIM_MDIER_MCMP2DE_Msk (0x1U << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
#define HRTIM_MDIER_MCMP3DE_Pos (18U)
#define HRTIM_MDIER_MCMP3DE_Msk (0x1U << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
#define HRTIM_MDIER_MCMP4DE_Pos (19U)
#define HRTIM_MDIER_MCMP4DE_Msk (0x1U << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
#define HRTIM_MDIER_MREPDE_Pos (20U)
#define HRTIM_MDIER_MREPDE_Msk (0x1U << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
#define HRTIM_MDIER_SYNCDE_Pos (21U)
#define HRTIM_MDIER_SYNCDE_Msk (0x1U << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
#define HRTIM_MDIER_MUPDDE_Pos (22U)
#define HRTIM_MDIER_MUPDDE_Msk (0x1U << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
/******************* Bit definition for HRTIM_MCNTR register ****************/
#define HRTIM_MCNTR_MCNTR_Pos (0U)
#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFU << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
/******************* Bit definition for HRTIM_MPER register *****************/
#define HRTIM_MPER_MPER_Pos (0U)
#define HRTIM_MPER_MPER_Msk (0xFFFFU << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
/******************* Bit definition for HRTIM_MREP register *****************/
#define HRTIM_MREP_MREP_Pos (0U)
#define HRTIM_MREP_MREP_Msk (0xFFU << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
/******************* Bit definition for HRTIM_MCMP1R register *****************/
#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFU << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP2R register *****************/
#define HRTIM_MCMP1R_MCMP2R_Pos (0U)
#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFU << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP3R register *****************/
#define HRTIM_MCMP1R_MCMP3R_Pos (0U)
#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFU << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP4R register *****************/
#define HRTIM_MCMP1R_MCMP4R_Pos (0U)
#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFU << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
/******************** Slave control register **********************************/
#define HRTIM_TIMCR_CK_PSC_Pos (0U)
#define HRTIM_TIMCR_CK_PSC_Msk (0x7U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
#define HRTIM_TIMCR_CK_PSC_0 (0x1U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
#define HRTIM_TIMCR_CK_PSC_1 (0x2U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
#define HRTIM_TIMCR_CK_PSC_2 (0x4U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
#define HRTIM_TIMCR_CONT_Pos (3U)
#define HRTIM_TIMCR_CONT_Msk (0x1U << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
#define HRTIM_TIMCR_RETRIG_Pos (4U)
#define HRTIM_TIMCR_RETRIG_Msk (0x1U << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
#define HRTIM_TIMCR_HALF_Pos (5U)
#define HRTIM_TIMCR_HALF_Msk (0x1U << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
#define HRTIM_TIMCR_PSHPLL_Pos (6U)
#define HRTIM_TIMCR_PSHPLL_Msk (0x1U << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
#define HRTIM_TIMCR_SYNCRST_Pos (10U)
#define HRTIM_TIMCR_SYNCRST_Msk (0x1U << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1U << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
#define HRTIM_TIMCR_DELCMP2_Pos (12U)
#define HRTIM_TIMCR_DELCMP2_Msk (0x3U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
#define HRTIM_TIMCR_DELCMP2_0 (0x1U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
#define HRTIM_TIMCR_DELCMP2_1 (0x2U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
#define HRTIM_TIMCR_DELCMP4_Pos (14U)
#define HRTIM_TIMCR_DELCMP4_Msk (0x3U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
#define HRTIM_TIMCR_DELCMP4_0 (0x1U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
#define HRTIM_TIMCR_DELCMP4_1 (0x2U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
#define HRTIM_TIMCR_TREPU_Pos (17U)
#define HRTIM_TIMCR_TREPU_Msk (0x1U << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
#define HRTIM_TIMCR_TRSTU_Pos (18U)
#define HRTIM_TIMCR_TRSTU_Msk (0x1U << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
#define HRTIM_TIMCR_TAU_Pos (19U)
#define HRTIM_TIMCR_TAU_Msk (0x1U << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
#define HRTIM_TIMCR_TBU_Pos (20U)
#define HRTIM_TIMCR_TBU_Msk (0x1U << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
#define HRTIM_TIMCR_TCU_Pos (21U)
#define HRTIM_TIMCR_TCU_Msk (0x1U << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
#define HRTIM_TIMCR_TDU_Pos (22U)
#define HRTIM_TIMCR_TDU_Msk (0x1U << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
#define HRTIM_TIMCR_TEU_Pos (23U)
#define HRTIM_TIMCR_TEU_Msk (0x1U << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
#define HRTIM_TIMCR_MSTU_Pos (24U)
#define HRTIM_TIMCR_MSTU_Msk (0x1U << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
#define HRTIM_TIMCR_DACSYNC_Msk (0x3U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
#define HRTIM_TIMCR_DACSYNC_0 (0x1U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
#define HRTIM_TIMCR_DACSYNC_1 (0x2U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
#define HRTIM_TIMCR_PREEN_Pos (27U)
#define HRTIM_TIMCR_PREEN_Msk (0x1U << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
#define HRTIM_TIMCR_UPDGAT_Pos (28U)
#define HRTIM_TIMCR_UPDGAT_Msk (0xFU << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
#define HRTIM_TIMCR_UPDGAT_0 (0x1U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
#define HRTIM_TIMCR_UPDGAT_1 (0x2U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
#define HRTIM_TIMCR_UPDGAT_2 (0x4U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
#define HRTIM_TIMCR_UPDGAT_3 (0x8U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
/******************** Slave Interrupt status register **************************/
#define HRTIM_TIMISR_CMP1_Pos (0U)
#define HRTIM_TIMISR_CMP1_Msk (0x1U << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
#define HRTIM_TIMISR_CMP2_Pos (1U)
#define HRTIM_TIMISR_CMP2_Msk (0x1U << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
#define HRTIM_TIMISR_CMP3_Pos (2U)
#define HRTIM_TIMISR_CMP3_Msk (0x1U << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
#define HRTIM_TIMISR_CMP4_Pos (3U)
#define HRTIM_TIMISR_CMP4_Msk (0x1U << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
#define HRTIM_TIMISR_REP_Pos (4U)
#define HRTIM_TIMISR_REP_Msk (0x1U << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
#define HRTIM_TIMISR_UPD_Pos (6U)
#define HRTIM_TIMISR_UPD_Msk (0x1U << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
#define HRTIM_TIMISR_CPT1_Pos (7U)
#define HRTIM_TIMISR_CPT1_Msk (0x1U << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
#define HRTIM_TIMISR_CPT2_Pos (8U)
#define HRTIM_TIMISR_CPT2_Msk (0x1U << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
#define HRTIM_TIMISR_SET1_Pos (9U)
#define HRTIM_TIMISR_SET1_Msk (0x1U << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
#define HRTIM_TIMISR_RST1_Pos (10U)
#define HRTIM_TIMISR_RST1_Msk (0x1U << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
#define HRTIM_TIMISR_SET2_Pos (11U)
#define HRTIM_TIMISR_SET2_Msk (0x1U << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
#define HRTIM_TIMISR_RST2_Pos (12U)
#define HRTIM_TIMISR_RST2_Msk (0x1U << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
#define HRTIM_TIMISR_RST_Pos (13U)
#define HRTIM_TIMISR_RST_Msk (0x1U << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
#define HRTIM_TIMISR_DLYPRT_Pos (14U)
#define HRTIM_TIMISR_DLYPRT_Msk (0x1U << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
#define HRTIM_TIMISR_CPPSTAT_Msk (0x1U << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
#define HRTIM_TIMISR_IPPSTAT_Msk (0x1U << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
#define HRTIM_TIMISR_O1STAT_Pos (18U)
#define HRTIM_TIMISR_O1STAT_Msk (0x1U << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
#define HRTIM_TIMISR_O2STAT_Pos (19U)
#define HRTIM_TIMISR_O2STAT_Msk (0x1U << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
#define HRTIM_TIMISR_O1CPY_Pos (20U)
#define HRTIM_TIMISR_O1CPY_Msk (0x1U << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
#define HRTIM_TIMISR_O2CPY_Pos (21U)
#define HRTIM_TIMISR_O2CPY_Msk (0x1U << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
/******************** Slave Interrupt clear register **************************/
#define HRTIM_TIMICR_CMP1C_Pos (0U)
#define HRTIM_TIMICR_CMP1C_Msk (0x1U << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
#define HRTIM_TIMICR_CMP2C_Pos (1U)
#define HRTIM_TIMICR_CMP2C_Msk (0x1U << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
#define HRTIM_TIMICR_CMP3C_Pos (2U)
#define HRTIM_TIMICR_CMP3C_Msk (0x1U << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
#define HRTIM_TIMICR_CMP4C_Pos (3U)
#define HRTIM_TIMICR_CMP4C_Msk (0x1U << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
#define HRTIM_TIMICR_REPC_Pos (4U)
#define HRTIM_TIMICR_REPC_Msk (0x1U << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
#define HRTIM_TIMICR_UPDC_Pos (6U)
#define HRTIM_TIMICR_UPDC_Msk (0x1U << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
#define HRTIM_TIMICR_CPT1C_Pos (7U)
#define HRTIM_TIMICR_CPT1C_Msk (0x1U << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
#define HRTIM_TIMICR_CPT2C_Pos (8U)
#define HRTIM_TIMICR_CPT2C_Msk (0x1U << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
#define HRTIM_TIMICR_SET1C_Pos (9U)
#define HRTIM_TIMICR_SET1C_Msk (0x1U << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
#define HRTIM_TIMICR_RST1C_Pos (10U)
#define HRTIM_TIMICR_RST1C_Msk (0x1U << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
#define HRTIM_TIMICR_SET2C_Pos (11U)
#define HRTIM_TIMICR_SET2C_Msk (0x1U << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
#define HRTIM_TIMICR_RST2C_Pos (12U)
#define HRTIM_TIMICR_RST2C_Msk (0x1U << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
#define HRTIM_TIMICR_RSTC_Pos (13U)
#define HRTIM_TIMICR_RSTC_Msk (0x1U << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
#define HRTIM_TIMICR_DLYPRTC_Msk (0x1U << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
/******************** Slave DMA/Interrupt enable register *********************/
#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
#define HRTIM_TIMDIER_CMP1IE_Msk (0x1U << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
#define HRTIM_TIMDIER_CMP2IE_Msk (0x1U << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
#define HRTIM_TIMDIER_CMP3IE_Msk (0x1U << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
#define HRTIM_TIMDIER_CMP4IE_Msk (0x1U << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
#define HRTIM_TIMDIER_REPIE_Pos (4U)
#define HRTIM_TIMDIER_REPIE_Msk (0x1U << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
#define HRTIM_TIMDIER_UPDIE_Pos (6U)
#define HRTIM_TIMDIER_UPDIE_Msk (0x1U << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
#define HRTIM_TIMDIER_CPT1IE_Msk (0x1U << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
#define HRTIM_TIMDIER_CPT2IE_Msk (0x1U << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
#define HRTIM_TIMDIER_SET1IE_Pos (9U)
#define HRTIM_TIMDIER_SET1IE_Msk (0x1U << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
#define HRTIM_TIMDIER_RST1IE_Pos (10U)
#define HRTIM_TIMDIER_RST1IE_Msk (0x1U << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
#define HRTIM_TIMDIER_SET2IE_Pos (11U)
#define HRTIM_TIMDIER_SET2IE_Msk (0x1U << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
#define HRTIM_TIMDIER_RST2IE_Pos (12U)
#define HRTIM_TIMDIER_RST2IE_Msk (0x1U << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
#define HRTIM_TIMDIER_RSTIE_Pos (13U)
#define HRTIM_TIMDIER_RSTIE_Msk (0x1U << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
#define HRTIM_TIMDIER_CMP1DE_Msk (0x1U << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
#define HRTIM_TIMDIER_CMP2DE_Msk (0x1U << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
#define HRTIM_TIMDIER_CMP3DE_Msk (0x1U << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
#define HRTIM_TIMDIER_CMP4DE_Msk (0x1U << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
#define HRTIM_TIMDIER_REPDE_Pos (20U)
#define HRTIM_TIMDIER_REPDE_Msk (0x1U << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
#define HRTIM_TIMDIER_UPDDE_Pos (22U)
#define HRTIM_TIMDIER_UPDDE_Msk (0x1U << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
#define HRTIM_TIMDIER_CPT1DE_Msk (0x1U << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
#define HRTIM_TIMDIER_CPT2DE_Msk (0x1U << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
#define HRTIM_TIMDIER_SET1DE_Pos (25U)
#define HRTIM_TIMDIER_SET1DE_Msk (0x1U << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
#define HRTIM_TIMDIER_RST1DE_Pos (26U)
#define HRTIM_TIMDIER_RST1DE_Msk (0x1U << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
#define HRTIM_TIMDIER_SET2DE_Pos (27U)
#define HRTIM_TIMDIER_SET2DE_Msk (0x1U << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
#define HRTIM_TIMDIER_RST2DE_Pos (28U)
#define HRTIM_TIMDIER_RST2DE_Msk (0x1U << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
#define HRTIM_TIMDIER_RSTDE_Pos (29U)
#define HRTIM_TIMDIER_RSTDE_Msk (0x1U << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
/****************** Bit definition for HRTIM_CNTR register ****************/
#define HRTIM_CNTR_CNTR_Pos (0U)
#define HRTIM_CNTR_CNTR_Msk (0xFFFFU << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
/******************* Bit definition for HRTIM_PER register *****************/
#define HRTIM_PER_PER_Pos (0U)
#define HRTIM_PER_PER_Msk (0xFFFFU << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
#define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
/******************* Bit definition for HRTIM_REP register *****************/
#define HRTIM_REP_REP_Pos (0U)
#define HRTIM_REP_REP_Msk (0xFFU << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
#define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
/******************* Bit definition for HRTIM_CMP1R register *****************/
#define HRTIM_CMP1R_CMP1R_Pos (0U)
#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFU << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP1CR register *****************/
#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFU << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP2R register *****************/
#define HRTIM_CMP2R_CMP2R_Pos (0U)
#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFU << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP3R register *****************/
#define HRTIM_CMP3R_CMP3R_Pos (0U)
#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFU << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP4R register *****************/
#define HRTIM_CMP4R_CMP4R_Pos (0U)
#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFU << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CPT1R register ****************/
#define HRTIM_CPT1R_CPT1R_Pos (0U)
#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFU << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
/******************* Bit definition for HRTIM_CPT2R register ****************/
#define HRTIM_CPT2R_CPT2R_Pos (0U)
#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFU << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
/******************** Bit definition for Slave Deadtime register **************/
#define HRTIM_DTR_DTR_Pos (0U)
#define HRTIM_DTR_DTR_Msk (0x1FFU << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
#define HRTIM_DTR_DTR_0 (0x001U << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
#define HRTIM_DTR_DTR_1 (0x002U << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
#define HRTIM_DTR_DTR_2 (0x004U << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
#define HRTIM_DTR_DTR_3 (0x008U << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
#define HRTIM_DTR_DTR_4 (0x010U << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
#define HRTIM_DTR_DTR_5 (0x020U << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
#define HRTIM_DTR_DTR_6 (0x040U << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
#define HRTIM_DTR_DTR_7 (0x080U << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
#define HRTIM_DTR_DTR_8 (0x100U << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
#define HRTIM_DTR_SDTR_Pos (9U)
#define HRTIM_DTR_SDTR_Msk (0x1U << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
#define HRTIM_DTR_DTPRSC_Pos (10U)
#define HRTIM_DTR_DTPRSC_Msk (0x7U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
#define HRTIM_DTR_DTPRSC_0 (0x1U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
#define HRTIM_DTR_DTPRSC_1 (0x2U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
#define HRTIM_DTR_DTPRSC_2 (0x4U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
#define HRTIM_DTR_DTRSLK_Pos (14U)
#define HRTIM_DTR_DTRSLK_Msk (0x1U << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
#define HRTIM_DTR_DTRLK_Pos (15U)
#define HRTIM_DTR_DTRLK_Msk (0x1U << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
#define HRTIM_DTR_DTF_Pos (16U)
#define HRTIM_DTR_DTF_Msk (0x1FFU << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
#define HRTIM_DTR_DTF_0 (0x001U << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
#define HRTIM_DTR_DTF_1 (0x002U << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
#define HRTIM_DTR_DTF_2 (0x004U << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
#define HRTIM_DTR_DTF_3 (0x008U << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
#define HRTIM_DTR_DTF_4 (0x010U << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
#define HRTIM_DTR_DTF_5 (0x020U << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
#define HRTIM_DTR_DTF_6 (0x040U << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
#define HRTIM_DTR_DTF_7 (0x080U << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
#define HRTIM_DTR_DTF_8 (0x100U << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
#define HRTIM_DTR_SDTF_Pos (25U)
#define HRTIM_DTR_SDTF_Msk (0x1U << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
#define HRTIM_DTR_DTFSLK_Pos (30U)
#define HRTIM_DTR_DTFSLK_Msk (0x1U << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
#define HRTIM_DTR_DTFLK_Pos (31U)
#define HRTIM_DTR_DTFLK_Msk (0x1U << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
/**** Bit definition for Slave Output 1 set register **************************/
#define HRTIM_SET1R_SST_Pos (0U)
#define HRTIM_SET1R_SST_Msk (0x1U << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
#define HRTIM_SET1R_RESYNC_Pos (1U)
#define HRTIM_SET1R_RESYNC_Msk (0x1U << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_SET1R_PER_Pos (2U)
#define HRTIM_SET1R_PER_Msk (0x1U << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
#define HRTIM_SET1R_CMP1_Pos (3U)
#define HRTIM_SET1R_CMP1_Msk (0x1U << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_SET1R_CMP2_Pos (4U)
#define HRTIM_SET1R_CMP2_Msk (0x1U << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_SET1R_CMP3_Pos (5U)
#define HRTIM_SET1R_CMP3_Msk (0x1U << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_SET1R_CMP4_Pos (6U)
#define HRTIM_SET1R_CMP4_Msk (0x1U << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_SET1R_MSTPER_Pos (7U)
#define HRTIM_SET1R_MSTPER_Msk (0x1U << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
#define HRTIM_SET1R_MSTCMP1_Pos (8U)
#define HRTIM_SET1R_MSTCMP1_Msk (0x1U << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_SET1R_MSTCMP2_Pos (9U)
#define HRTIM_SET1R_MSTCMP2_Msk (0x1U << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_SET1R_MSTCMP3_Pos (10U)
#define HRTIM_SET1R_MSTCMP3_Msk (0x1U << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_SET1R_MSTCMP4_Pos (11U)
#define HRTIM_SET1R_MSTCMP4_Msk (0x1U << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
#define HRTIM_SET1R_TIMEVNT1_Msk (0x1U << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
#define HRTIM_SET1R_TIMEVNT2_Msk (0x1U << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
#define HRTIM_SET1R_TIMEVNT3_Msk (0x1U << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
#define HRTIM_SET1R_TIMEVNT4_Msk (0x1U << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
#define HRTIM_SET1R_TIMEVNT5_Msk (0x1U << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
#define HRTIM_SET1R_TIMEVNT6_Msk (0x1U << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
#define HRTIM_SET1R_TIMEVNT7_Msk (0x1U << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
#define HRTIM_SET1R_TIMEVNT8_Msk (0x1U << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
#define HRTIM_SET1R_TIMEVNT9_Msk (0x1U << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_SET1R_EXTVNT1_Pos (21U)
#define HRTIM_SET1R_EXTVNT1_Msk (0x1U << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_SET1R_EXTVNT2_Pos (22U)
#define HRTIM_SET1R_EXTVNT2_Msk (0x1U << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_SET1R_EXTVNT3_Pos (23U)
#define HRTIM_SET1R_EXTVNT3_Msk (0x1U << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_SET1R_EXTVNT4_Pos (24U)
#define HRTIM_SET1R_EXTVNT4_Msk (0x1U << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_SET1R_EXTVNT5_Pos (25U)
#define HRTIM_SET1R_EXTVNT5_Msk (0x1U << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_SET1R_EXTVNT6_Pos (26U)
#define HRTIM_SET1R_EXTVNT6_Msk (0x1U << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_SET1R_EXTVNT7_Pos (27U)
#define HRTIM_SET1R_EXTVNT7_Msk (0x1U << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_SET1R_EXTVNT8_Pos (28U)
#define HRTIM_SET1R_EXTVNT8_Msk (0x1U << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_SET1R_EXTVNT9_Pos (29U)
#define HRTIM_SET1R_EXTVNT9_Msk (0x1U << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_SET1R_EXTVNT10_Pos (30U)
#define HRTIM_SET1R_EXTVNT10_Msk (0x1U << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_SET1R_UPDATE_Pos (31U)
#define HRTIM_SET1R_UPDATE_Msk (0x1U << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 1 reset register ************************/
#define HRTIM_RST1R_SRT_Pos (0U)
#define HRTIM_RST1R_SRT_Msk (0x1U << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
#define HRTIM_RST1R_RESYNC_Pos (1U)
#define HRTIM_RST1R_RESYNC_Msk (0x1U << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_RST1R_PER_Pos (2U)
#define HRTIM_RST1R_PER_Msk (0x1U << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
#define HRTIM_RST1R_CMP1_Pos (3U)
#define HRTIM_RST1R_CMP1_Msk (0x1U << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RST1R_CMP2_Pos (4U)
#define HRTIM_RST1R_CMP2_Msk (0x1U << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RST1R_CMP3_Pos (5U)
#define HRTIM_RST1R_CMP3_Msk (0x1U << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_RST1R_CMP4_Pos (6U)
#define HRTIM_RST1R_CMP4_Msk (0x1U << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RST1R_MSTPER_Pos (7U)
#define HRTIM_RST1R_MSTPER_Msk (0x1U << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
#define HRTIM_RST1R_MSTCMP1_Pos (8U)
#define HRTIM_RST1R_MSTCMP1_Msk (0x1U << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_RST1R_MSTCMP2_Pos (9U)
#define HRTIM_RST1R_MSTCMP2_Msk (0x1U << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_RST1R_MSTCMP3_Pos (10U)
#define HRTIM_RST1R_MSTCMP3_Msk (0x1U << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_RST1R_MSTCMP4_Pos (11U)
#define HRTIM_RST1R_MSTCMP4_Msk (0x1U << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
#define HRTIM_RST1R_TIMEVNT1_Msk (0x1U << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
#define HRTIM_RST1R_TIMEVNT2_Msk (0x1U << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
#define HRTIM_RST1R_TIMEVNT3_Msk (0x1U << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
#define HRTIM_RST1R_TIMEVNT4_Msk (0x1U << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
#define HRTIM_RST1R_TIMEVNT5_Msk (0x1U << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
#define HRTIM_RST1R_TIMEVNT6_Msk (0x1U << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
#define HRTIM_RST1R_TIMEVNT7_Msk (0x1U << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
#define HRTIM_RST1R_TIMEVNT8_Msk (0x1U << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
#define HRTIM_RST1R_TIMEVNT9_Msk (0x1U << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_RST1R_EXTVNT1_Pos (21U)
#define HRTIM_RST1R_EXTVNT1_Msk (0x1U << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_RST1R_EXTVNT2_Pos (22U)
#define HRTIM_RST1R_EXTVNT2_Msk (0x1U << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_RST1R_EXTVNT3_Pos (23U)
#define HRTIM_RST1R_EXTVNT3_Msk (0x1U << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_RST1R_EXTVNT4_Pos (24U)
#define HRTIM_RST1R_EXTVNT4_Msk (0x1U << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_RST1R_EXTVNT5_Pos (25U)
#define HRTIM_RST1R_EXTVNT5_Msk (0x1U << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_RST1R_EXTVNT6_Pos (26U)
#define HRTIM_RST1R_EXTVNT6_Msk (0x1U << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_RST1R_EXTVNT7_Pos (27U)
#define HRTIM_RST1R_EXTVNT7_Msk (0x1U << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_RST1R_EXTVNT8_Pos (28U)
#define HRTIM_RST1R_EXTVNT8_Msk (0x1U << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_RST1R_EXTVNT9_Pos (29U)
#define HRTIM_RST1R_EXTVNT9_Msk (0x1U << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_RST1R_EXTVNT10_Pos (30U)
#define HRTIM_RST1R_EXTVNT10_Msk (0x1U << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_RST1R_UPDATE_Pos (31U)
#define HRTIM_RST1R_UPDATE_Msk (0x1U << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 2 set register **************************/
#define HRTIM_SET2R_SST_Pos (0U)
#define HRTIM_SET2R_SST_Msk (0x1U << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
#define HRTIM_SET2R_RESYNC_Pos (1U)
#define HRTIM_SET2R_RESYNC_Msk (0x1U << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_SET2R_PER_Pos (2U)
#define HRTIM_SET2R_PER_Msk (0x1U << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
#define HRTIM_SET2R_CMP1_Pos (3U)
#define HRTIM_SET2R_CMP1_Msk (0x1U << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_SET2R_CMP2_Pos (4U)
#define HRTIM_SET2R_CMP2_Msk (0x1U << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_SET2R_CMP3_Pos (5U)
#define HRTIM_SET2R_CMP3_Msk (0x1U << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_SET2R_CMP4_Pos (6U)
#define HRTIM_SET2R_CMP4_Msk (0x1U << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_SET2R_MSTPER_Pos (7U)
#define HRTIM_SET2R_MSTPER_Msk (0x1U << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
#define HRTIM_SET2R_MSTCMP1_Pos (8U)
#define HRTIM_SET2R_MSTCMP1_Msk (0x1U << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_SET2R_MSTCMP2_Pos (9U)
#define HRTIM_SET2R_MSTCMP2_Msk (0x1U << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_SET2R_MSTCMP3_Pos (10U)
#define HRTIM_SET2R_MSTCMP3_Msk (0x1U << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_SET2R_MSTCMP4_Pos (11U)
#define HRTIM_SET2R_MSTCMP4_Msk (0x1U << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
#define HRTIM_SET2R_TIMEVNT1_Msk (0x1U << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
#define HRTIM_SET2R_TIMEVNT2_Msk (0x1U << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
#define HRTIM_SET2R_TIMEVNT3_Msk (0x1U << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
#define HRTIM_SET2R_TIMEVNT4_Msk (0x1U << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
#define HRTIM_SET2R_TIMEVNT5_Msk (0x1U << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
#define HRTIM_SET2R_TIMEVNT6_Msk (0x1U << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
#define HRTIM_SET2R_TIMEVNT7_Msk (0x1U << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
#define HRTIM_SET2R_TIMEVNT8_Msk (0x1U << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
#define HRTIM_SET2R_TIMEVNT9_Msk (0x1U << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_SET2R_EXTVNT1_Pos (21U)
#define HRTIM_SET2R_EXTVNT1_Msk (0x1U << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_SET2R_EXTVNT2_Pos (22U)
#define HRTIM_SET2R_EXTVNT2_Msk (0x1U << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_SET2R_EXTVNT3_Pos (23U)
#define HRTIM_SET2R_EXTVNT3_Msk (0x1U << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_SET2R_EXTVNT4_Pos (24U)
#define HRTIM_SET2R_EXTVNT4_Msk (0x1U << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_SET2R_EXTVNT5_Pos (25U)
#define HRTIM_SET2R_EXTVNT5_Msk (0x1U << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_SET2R_EXTVNT6_Pos (26U)
#define HRTIM_SET2R_EXTVNT6_Msk (0x1U << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_SET2R_EXTVNT7_Pos (27U)
#define HRTIM_SET2R_EXTVNT7_Msk (0x1U << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_SET2R_EXTVNT8_Pos (28U)
#define HRTIM_SET2R_EXTVNT8_Msk (0x1U << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_SET2R_EXTVNT9_Pos (29U)
#define HRTIM_SET2R_EXTVNT9_Msk (0x1U << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_SET2R_EXTVNT10_Pos (30U)
#define HRTIM_SET2R_EXTVNT10_Msk (0x1U << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_SET2R_UPDATE_Pos (31U)
#define HRTIM_SET2R_UPDATE_Msk (0x1U << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 2 reset register ************************/
#define HRTIM_RST2R_SRT_Pos (0U)
#define HRTIM_RST2R_SRT_Msk (0x1U << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
#define HRTIM_RST2R_RESYNC_Pos (1U)
#define HRTIM_RST2R_RESYNC_Msk (0x1U << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_RST2R_PER_Pos (2U)
#define HRTIM_RST2R_PER_Msk (0x1U << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
#define HRTIM_RST2R_CMP1_Pos (3U)
#define HRTIM_RST2R_CMP1_Msk (0x1U << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RST2R_CMP2_Pos (4U)
#define HRTIM_RST2R_CMP2_Msk (0x1U << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RST2R_CMP3_Pos (5U)
#define HRTIM_RST2R_CMP3_Msk (0x1U << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_RST2R_CMP4_Pos (6U)
#define HRTIM_RST2R_CMP4_Msk (0x1U << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RST2R_MSTPER_Pos (7U)
#define HRTIM_RST2R_MSTPER_Msk (0x1U << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
#define HRTIM_RST2R_MSTCMP1_Pos (8U)
#define HRTIM_RST2R_MSTCMP1_Msk (0x1U << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_RST2R_MSTCMP2_Pos (9U)
#define HRTIM_RST2R_MSTCMP2_Msk (0x1U << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_RST2R_MSTCMP3_Pos (10U)
#define HRTIM_RST2R_MSTCMP3_Msk (0x1U << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_RST2R_MSTCMP4_Pos (11U)
#define HRTIM_RST2R_MSTCMP4_Msk (0x1U << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
#define HRTIM_RST2R_TIMEVNT1_Msk (0x1U << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
#define HRTIM_RST2R_TIMEVNT2_Msk (0x1U << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
#define HRTIM_RST2R_TIMEVNT3_Msk (0x1U << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
#define HRTIM_RST2R_TIMEVNT4_Msk (0x1U << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
#define HRTIM_RST2R_TIMEVNT5_Msk (0x1U << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
#define HRTIM_RST2R_TIMEVNT6_Msk (0x1U << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
#define HRTIM_RST2R_TIMEVNT7_Msk (0x1U << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
#define HRTIM_RST2R_TIMEVNT8_Msk (0x1U << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
#define HRTIM_RST2R_TIMEVNT9_Msk (0x1U << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_RST2R_EXTVNT1_Pos (21U)
#define HRTIM_RST2R_EXTVNT1_Msk (0x1U << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_RST2R_EXTVNT2_Pos (22U)
#define HRTIM_RST2R_EXTVNT2_Msk (0x1U << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_RST2R_EXTVNT3_Pos (23U)
#define HRTIM_RST2R_EXTVNT3_Msk (0x1U << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_RST2R_EXTVNT4_Pos (24U)
#define HRTIM_RST2R_EXTVNT4_Msk (0x1U << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_RST2R_EXTVNT5_Pos (25U)
#define HRTIM_RST2R_EXTVNT5_Msk (0x1U << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_RST2R_EXTVNT6_Pos (26U)
#define HRTIM_RST2R_EXTVNT6_Msk (0x1U << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_RST2R_EXTVNT7_Pos (27U)
#define HRTIM_RST2R_EXTVNT7_Msk (0x1U << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_RST2R_EXTVNT8_Pos (28U)
#define HRTIM_RST2R_EXTVNT8_Msk (0x1U << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_RST2R_EXTVNT9_Pos (29U)
#define HRTIM_RST2R_EXTVNT9_Msk (0x1U << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_RST2R_EXTVNT10_Pos (30U)
#define HRTIM_RST2R_EXTVNT10_Msk (0x1U << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_RST2R_UPDATE_Pos (31U)
#define HRTIM_RST2R_UPDATE_Msk (0x1U << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave external event filtering register 1 ***********/
#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
#define HRTIM_EEFR1_EE1LTCH_Msk (0x1U << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
#define HRTIM_EEFR1_EE1FLTR_Msk (0xFU << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
#define HRTIM_EEFR1_EE1FLTR_0 (0x1U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
#define HRTIM_EEFR1_EE1FLTR_1 (0x2U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
#define HRTIM_EEFR1_EE1FLTR_2 (0x4U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
#define HRTIM_EEFR1_EE1FLTR_3 (0x8U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
#define HRTIM_EEFR1_EE2LTCH_Msk (0x1U << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
#define HRTIM_EEFR1_EE2FLTR_Msk (0xFU << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
#define HRTIM_EEFR1_EE2FLTR_0 (0x1U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
#define HRTIM_EEFR1_EE2FLTR_1 (0x2U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
#define HRTIM_EEFR1_EE2FLTR_2 (0x4U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
#define HRTIM_EEFR1_EE2FLTR_3 (0x8U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
#define HRTIM_EEFR1_EE3LTCH_Msk (0x1U << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
#define HRTIM_EEFR1_EE3FLTR_Msk (0xFU << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
#define HRTIM_EEFR1_EE3FLTR_0 (0x1U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
#define HRTIM_EEFR1_EE3FLTR_1 (0x2U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
#define HRTIM_EEFR1_EE3FLTR_2 (0x4U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
#define HRTIM_EEFR1_EE3FLTR_3 (0x8U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
#define HRTIM_EEFR1_EE4LTCH_Msk (0x1U << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
#define HRTIM_EEFR1_EE4FLTR_Msk (0xFU << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
#define HRTIM_EEFR1_EE4FLTR_0 (0x1U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
#define HRTIM_EEFR1_EE4FLTR_1 (0x2U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
#define HRTIM_EEFR1_EE4FLTR_2 (0x4U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
#define HRTIM_EEFR1_EE4FLTR_3 (0x8U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
#define HRTIM_EEFR1_EE5LTCH_Msk (0x1U << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
#define HRTIM_EEFR1_EE5FLTR_Msk (0xFU << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
#define HRTIM_EEFR1_EE5FLTR_0 (0x1U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
#define HRTIM_EEFR1_EE5FLTR_1 (0x2U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
#define HRTIM_EEFR1_EE5FLTR_2 (0x4U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
#define HRTIM_EEFR1_EE5FLTR_3 (0x8U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
/**** Bit definition for Slave external event filtering register 2 ***********/
#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
#define HRTIM_EEFR2_EE6LTCH_Msk (0x1U << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
#define HRTIM_EEFR2_EE6FLTR_Msk (0xFU << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
#define HRTIM_EEFR2_EE6FLTR_0 (0x1U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
#define HRTIM_EEFR2_EE6FLTR_1 (0x2U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
#define HRTIM_EEFR2_EE6FLTR_2 (0x4U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
#define HRTIM_EEFR2_EE6FLTR_3 (0x8U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
#define HRTIM_EEFR2_EE7LTCH_Msk (0x1U << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
#define HRTIM_EEFR2_EE7FLTR_Msk (0xFU << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
#define HRTIM_EEFR2_EE7FLTR_0 (0x1U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
#define HRTIM_EEFR2_EE7FLTR_1 (0x2U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
#define HRTIM_EEFR2_EE7FLTR_2 (0x4U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
#define HRTIM_EEFR2_EE7FLTR_3 (0x8U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
#define HRTIM_EEFR2_EE8LTCH_Msk (0x1U << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
#define HRTIM_EEFR2_EE8FLTR_Msk (0xFU << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
#define HRTIM_EEFR2_EE8FLTR_0 (0x1U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
#define HRTIM_EEFR2_EE8FLTR_1 (0x2U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
#define HRTIM_EEFR2_EE8FLTR_2 (0x4U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
#define HRTIM_EEFR2_EE8FLTR_3 (0x8U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
#define HRTIM_EEFR2_EE9LTCH_Msk (0x1U << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
#define HRTIM_EEFR2_EE9FLTR_Msk (0xFU << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
#define HRTIM_EEFR2_EE9FLTR_0 (0x1U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
#define HRTIM_EEFR2_EE9FLTR_1 (0x2U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
#define HRTIM_EEFR2_EE9FLTR_2 (0x4U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
#define HRTIM_EEFR2_EE9FLTR_3 (0x8U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
#define HRTIM_EEFR2_EE10LTCH_Msk (0x1U << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
#define HRTIM_EEFR2_EE10FLTR_Msk (0xFU << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
#define HRTIM_EEFR2_EE10FLTR_0 (0x1U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
#define HRTIM_EEFR2_EE10FLTR_1 (0x2U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
#define HRTIM_EEFR2_EE10FLTR_2 (0x4U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
#define HRTIM_EEFR2_EE10FLTR_3 (0x8U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
/**** Bit definition for Slave Timer reset register ***************************/
#define HRTIM_RSTR_UPDATE_Pos (1U)
#define HRTIM_RSTR_UPDATE_Msk (0x1U << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
#define HRTIM_RSTR_CMP2_Pos (2U)
#define HRTIM_RSTR_CMP2_Msk (0x1U << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
#define HRTIM_RSTR_CMP4_Pos (3U)
#define HRTIM_RSTR_CMP4_Msk (0x1U << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
#define HRTIM_RSTR_MSTPER_Pos (4U)
#define HRTIM_RSTR_MSTPER_Msk (0x1U << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
#define HRTIM_RSTR_MSTCMP1_Pos (5U)
#define HRTIM_RSTR_MSTCMP1_Msk (0x1U << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
#define HRTIM_RSTR_MSTCMP2_Pos (6U)
#define HRTIM_RSTR_MSTCMP2_Msk (0x1U << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
#define HRTIM_RSTR_MSTCMP3_Pos (7U)
#define HRTIM_RSTR_MSTCMP3_Msk (0x1U << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
#define HRTIM_RSTR_MSTCMP4_Pos (8U)
#define HRTIM_RSTR_MSTCMP4_Msk (0x1U << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
#define HRTIM_RSTR_EXTEVNT1_Msk (0x1U << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
#define HRTIM_RSTR_EXTEVNT2_Msk (0x1U << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
#define HRTIM_RSTR_EXTEVNT3_Msk (0x1U << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
#define HRTIM_RSTR_EXTEVNT4_Msk (0x1U << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
#define HRTIM_RSTR_EXTEVNT5_Msk (0x1U << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
#define HRTIM_RSTR_EXTEVNT6_Msk (0x1U << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
#define HRTIM_RSTR_EXTEVNT7_Msk (0x1U << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
#define HRTIM_RSTR_EXTEVNT8_Msk (0x1U << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
#define HRTIM_RSTR_EXTEVNT9_Msk (0x1U << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1U << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1U << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
#define HRTIM_RSTR_TIMBCMP2_Msk (0x1U << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1U << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1U << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
#define HRTIM_RSTR_TIMCCMP2_Msk (0x1U << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1U << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1U << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTR_TIMDCMP2_Msk (0x1U << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1U << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1U << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTR_TIMECMP2_Pos (29U)
#define HRTIM_RSTR_TIMECMP2_Msk (0x1U << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1U << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
/**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFU << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
#define HRTIM_CHPR_CARFRQ_0 (0x1U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
#define HRTIM_CHPR_CARFRQ_1 (0x2U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
#define HRTIM_CHPR_CARFRQ_2 (0x4U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
#define HRTIM_CHPR_CARFRQ_3 (0x8U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
#define HRTIM_CHPR_CARDTY_Pos (4U)
#define HRTIM_CHPR_CARDTY_Msk (0x7U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
#define HRTIM_CHPR_CARDTY_0 (0x1U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
#define HRTIM_CHPR_CARDTY_1 (0x2U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
#define HRTIM_CHPR_CARDTY_2 (0x4U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
#define HRTIM_CHPR_STRPW_Pos (7U)
#define HRTIM_CHPR_STRPW_Msk (0xFU << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
#define HRTIM_CHPR_STRPW_0 (0x1U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
#define HRTIM_CHPR_STRPW_1 (0x2U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
#define HRTIM_CHPR_STRPW_2 (0x4U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
#define HRTIM_CHPR_STRPW_3 (0x8U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
/**** Bit definition for Slave Timer Capture 1 control register ***************/
#define HRTIM_CPT1CR_SWCPT_Pos (0U)
#define HRTIM_CPT1CR_SWCPT_Msk (0x1U << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
#define HRTIM_CPT1CR_UPDCPT_Msk (0x1U << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
#define HRTIM_CPT1CR_TA1SET_Pos (12U)
#define HRTIM_CPT1CR_TA1SET_Msk (0x1U << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
#define HRTIM_CPT1CR_TA1RST_Pos (13U)
#define HRTIM_CPT1CR_TA1RST_Msk (0x1U << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1U << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1U << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_CPT1CR_TB1SET_Pos (16U)
#define HRTIM_CPT1CR_TB1SET_Msk (0x1U << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
#define HRTIM_CPT1CR_TB1RST_Pos (17U)
#define HRTIM_CPT1CR_TB1RST_Msk (0x1U << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_CPT1CR_TC1SET_Pos (20U)
#define HRTIM_CPT1CR_TC1SET_Msk (0x1U << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
#define HRTIM_CPT1CR_TC1RST_Pos (21U)
#define HRTIM_CPT1CR_TC1RST_Msk (0x1U << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_CPT1CR_TD1SET_Pos (24U)
#define HRTIM_CPT1CR_TD1SET_Msk (0x1U << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
#define HRTIM_CPT1CR_TD1RST_Pos (25U)
#define HRTIM_CPT1CR_TD1RST_Msk (0x1U << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_CPT1CR_TE1SET_Pos (28U)
#define HRTIM_CPT1CR_TE1SET_Msk (0x1U << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
#define HRTIM_CPT1CR_TE1RST_Pos (29U)
#define HRTIM_CPT1CR_TE1RST_Msk (0x1U << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1U << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1U << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Capture 2 control register ***************/
#define HRTIM_CPT2CR_SWCPT_Pos (0U)
#define HRTIM_CPT2CR_SWCPT_Msk (0x1U << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
#define HRTIM_CPT2CR_UPDCPT_Msk (0x1U << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
#define HRTIM_CPT2CR_TA1SET_Pos (12U)
#define HRTIM_CPT2CR_TA1SET_Msk (0x1U << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
#define HRTIM_CPT2CR_TA1RST_Pos (13U)
#define HRTIM_CPT2CR_TA1RST_Msk (0x1U << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1U << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1U << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_CPT2CR_TB1SET_Pos (16U)
#define HRTIM_CPT2CR_TB1SET_Msk (0x1U << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
#define HRTIM_CPT2CR_TB1RST_Pos (17U)
#define HRTIM_CPT2CR_TB1RST_Msk (0x1U << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_CPT2CR_TC1SET_Pos (20U)
#define HRTIM_CPT2CR_TC1SET_Msk (0x1U << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
#define HRTIM_CPT2CR_TC1RST_Pos (21U)
#define HRTIM_CPT2CR_TC1RST_Msk (0x1U << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_CPT2CR_TD1SET_Pos (24U)
#define HRTIM_CPT2CR_TD1SET_Msk (0x1U << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
#define HRTIM_CPT2CR_TD1RST_Pos (25U)
#define HRTIM_CPT2CR_TD1RST_Msk (0x1U << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_CPT2CR_TE1SET_Pos (28U)
#define HRTIM_CPT2CR_TE1SET_Msk (0x1U << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
#define HRTIM_CPT2CR_TE1RST_Pos (29U)
#define HRTIM_CPT2CR_TE1RST_Msk (0x1U << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1U << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1U << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Output register **************************/
#define HRTIM_OUTR_POL1_Pos (1U)
#define HRTIM_OUTR_POL1_Msk (0x1U << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
#define HRTIM_OUTR_IDLM1_Pos (2U)
#define HRTIM_OUTR_IDLM1_Msk (0x1U << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
#define HRTIM_OUTR_IDLES1_Pos (3U)
#define HRTIM_OUTR_IDLES1_Msk (0x1U << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
#define HRTIM_OUTR_FAULT1_Pos (4U)
#define HRTIM_OUTR_FAULT1_Msk (0x3U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
#define HRTIM_OUTR_FAULT1_0 (0x1U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
#define HRTIM_OUTR_FAULT1_1 (0x2U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
#define HRTIM_OUTR_CHP1_Pos (6U)
#define HRTIM_OUTR_CHP1_Msk (0x1U << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
#define HRTIM_OUTR_DIDL1_Pos (7U)
#define HRTIM_OUTR_DIDL1_Msk (0x1U << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
#define HRTIM_OUTR_DTEN_Pos (8U)
#define HRTIM_OUTR_DTEN_Msk (0x1U << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
#define HRTIM_OUTR_DLYPRTEN_Msk (0x1U << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
#define HRTIM_OUTR_DLYPRT_Pos (10U)
#define HRTIM_OUTR_DLYPRT_Msk (0x7U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
#define HRTIM_OUTR_DLYPRT_0 (0x1U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
#define HRTIM_OUTR_DLYPRT_1 (0x2U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
#define HRTIM_OUTR_DLYPRT_2 (0x4U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
#define HRTIM_OUTR_POL2_Pos (17U)
#define HRTIM_OUTR_POL2_Msk (0x1U << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
#define HRTIM_OUTR_IDLM2_Pos (18U)
#define HRTIM_OUTR_IDLM2_Msk (0x1U << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
#define HRTIM_OUTR_IDLES2_Pos (19U)
#define HRTIM_OUTR_IDLES2_Msk (0x1U << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
#define HRTIM_OUTR_FAULT2_Pos (20U)
#define HRTIM_OUTR_FAULT2_Msk (0x3U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
#define HRTIM_OUTR_FAULT2_0 (0x1U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
#define HRTIM_OUTR_FAULT2_1 (0x2U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
#define HRTIM_OUTR_CHP2_Pos (22U)
#define HRTIM_OUTR_CHP2_Msk (0x1U << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
#define HRTIM_OUTR_DIDL2_Pos (23U)
#define HRTIM_OUTR_DIDL2_Msk (0x1U << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
/**** Bit definition for Slave Timer Fault register ***************************/
#define HRTIM_FLTR_FLT1EN_Pos (0U)
#define HRTIM_FLTR_FLT1EN_Msk (0x1U << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
#define HRTIM_FLTR_FLT2EN_Pos (1U)
#define HRTIM_FLTR_FLT2EN_Msk (0x1U << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
#define HRTIM_FLTR_FLT3EN_Pos (2U)
#define HRTIM_FLTR_FLT3EN_Msk (0x1U << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
#define HRTIM_FLTR_FLT4EN_Pos (3U)
#define HRTIM_FLTR_FLT4EN_Msk (0x1U << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
#define HRTIM_FLTR_FLT5EN_Pos (4U)
#define HRTIM_FLTR_FLT5EN_Msk (0x1U << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
#define HRTIM_FLTR_FLTLCK_Pos (31U)
#define HRTIM_FLTR_FLTLCK_Msk (0x1U << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
/**** Bit definition for Common HRTIM Timer control register 1 ****************/
#define HRTIM_CR1_MUDIS_Pos (0U)
#define HRTIM_CR1_MUDIS_Msk (0x1U << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
#define HRTIM_CR1_TAUDIS_Pos (1U)
#define HRTIM_CR1_TAUDIS_Msk (0x1U << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
#define HRTIM_CR1_TBUDIS_Pos (2U)
#define HRTIM_CR1_TBUDIS_Msk (0x1U << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
#define HRTIM_CR1_TCUDIS_Pos (3U)
#define HRTIM_CR1_TCUDIS_Msk (0x1U << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
#define HRTIM_CR1_TDUDIS_Pos (4U)
#define HRTIM_CR1_TDUDIS_Msk (0x1U << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
#define HRTIM_CR1_TEUDIS_Pos (5U)
#define HRTIM_CR1_TEUDIS_Msk (0x1U << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
#define HRTIM_CR1_ADC1USRC_Pos (16U)
#define HRTIM_CR1_ADC1USRC_Msk (0x7U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
#define HRTIM_CR1_ADC1USRC_0 (0x1U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
#define HRTIM_CR1_ADC1USRC_1 (0x2U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
#define HRTIM_CR1_ADC1USRC_2 (0x4U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
#define HRTIM_CR1_ADC2USRC_Pos (19U)
#define HRTIM_CR1_ADC2USRC_Msk (0x7U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
#define HRTIM_CR1_ADC2USRC_0 (0x1U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
#define HRTIM_CR1_ADC2USRC_1 (0x2U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
#define HRTIM_CR1_ADC2USRC_2 (0x4U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
#define HRTIM_CR1_ADC3USRC_Pos (22U)
#define HRTIM_CR1_ADC3USRC_Msk (0x7U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
#define HRTIM_CR1_ADC3USRC_0 (0x1U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
#define HRTIM_CR1_ADC3USRC_1 (0x2U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
#define HRTIM_CR1_ADC3USRC_2 (0x4U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
#define HRTIM_CR1_ADC4USRC_Pos (25U)
#define HRTIM_CR1_ADC4USRC_Msk (0x7U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
#define HRTIM_CR1_ADC4USRC_0 (0x1U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
#define HRTIM_CR1_ADC4USRC_1 (0x2U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
#define HRTIM_CR1_ADC4USRC_2 (0x0U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
/**** Bit definition for Common HRTIM Timer control register 2 ****************/
#define HRTIM_CR2_MSWU_Pos (0U)
#define HRTIM_CR2_MSWU_Msk (0x1U << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
#define HRTIM_CR2_TASWU_Pos (1U)
#define HRTIM_CR2_TASWU_Msk (0x1U << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
#define HRTIM_CR2_TBSWU_Pos (2U)
#define HRTIM_CR2_TBSWU_Msk (0x1U << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
#define HRTIM_CR2_TCSWU_Pos (3U)
#define HRTIM_CR2_TCSWU_Msk (0x1U << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
#define HRTIM_CR2_TDSWU_Pos (4U)
#define HRTIM_CR2_TDSWU_Msk (0x1U << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
#define HRTIM_CR2_TESWU_Pos (5U)
#define HRTIM_CR2_TESWU_Msk (0x1U << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
#define HRTIM_CR2_MRST_Pos (8U)
#define HRTIM_CR2_MRST_Msk (0x1U << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
#define HRTIM_CR2_TARST_Pos (9U)
#define HRTIM_CR2_TARST_Msk (0x1U << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
#define HRTIM_CR2_TBRST_Pos (10U)
#define HRTIM_CR2_TBRST_Msk (0x1U << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
#define HRTIM_CR2_TCRST_Pos (11U)
#define HRTIM_CR2_TCRST_Msk (0x1U << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
#define HRTIM_CR2_TDRST_Pos (12U)
#define HRTIM_CR2_TDRST_Msk (0x1U << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
#define HRTIM_CR2_TERST_Pos (13U)
#define HRTIM_CR2_TERST_Msk (0x1U << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
/**** Bit definition for Common HRTIM Timer interrupt status register *********/
#define HRTIM_ISR_FLT1_Pos (0U)
#define HRTIM_ISR_FLT1_Msk (0x1U << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
#define HRTIM_ISR_FLT2_Pos (1U)
#define HRTIM_ISR_FLT2_Msk (0x1U << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
#define HRTIM_ISR_FLT3_Pos (2U)
#define HRTIM_ISR_FLT3_Msk (0x1U << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
#define HRTIM_ISR_FLT4_Pos (3U)
#define HRTIM_ISR_FLT4_Msk (0x1U << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
#define HRTIM_ISR_FLT5_Pos (4U)
#define HRTIM_ISR_FLT5_Msk (0x1U << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
#define HRTIM_ISR_SYSFLT_Pos (5U)
#define HRTIM_ISR_SYSFLT_Msk (0x1U << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
#define HRTIM_ISR_BMPER_Pos (17U)
#define HRTIM_ISR_BMPER_Msk (0x1U << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
#define HRTIM_ICR_FLT1C_Pos (0U)
#define HRTIM_ICR_FLT1C_Msk (0x1U << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
#define HRTIM_ICR_FLT2C_Pos (1U)
#define HRTIM_ICR_FLT2C_Msk (0x1U << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
#define HRTIM_ICR_FLT3C_Pos (2U)
#define HRTIM_ICR_FLT3C_Msk (0x1U << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
#define HRTIM_ICR_FLT4C_Pos (3U)
#define HRTIM_ICR_FLT4C_Msk (0x1U << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
#define HRTIM_ICR_FLT5C_Pos (4U)
#define HRTIM_ICR_FLT5C_Msk (0x1U << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
#define HRTIM_ICR_SYSFLTC_Pos (5U)
#define HRTIM_ICR_SYSFLTC_Msk (0x1U << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
#define HRTIM_ICR_BMPERC_Pos (17U)
#define HRTIM_ICR_BMPERC_Msk (0x1U << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
#define HRTIM_IER_FLT1_Pos (0U)
#define HRTIM_IER_FLT1_Msk (0x1U << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
#define HRTIM_IER_FLT2_Pos (1U)
#define HRTIM_IER_FLT2_Msk (0x1U << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
#define HRTIM_IER_FLT3_Pos (2U)
#define HRTIM_IER_FLT3_Msk (0x1U << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
#define HRTIM_IER_FLT4_Pos (3U)
#define HRTIM_IER_FLT4_Msk (0x1U << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
#define HRTIM_IER_FLT5_Pos (4U)
#define HRTIM_IER_FLT5_Msk (0x1U << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
#define HRTIM_IER_SYSFLT_Pos (5U)
#define HRTIM_IER_SYSFLT_Msk (0x1U << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
#define HRTIM_IER_BMPER_Pos (17U)
#define HRTIM_IER_BMPER_Msk (0x1U << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
/**** Bit definition for Common HRTIM Timer output enable register ************/
#define HRTIM_OENR_TA1OEN_Pos (0U)
#define HRTIM_OENR_TA1OEN_Msk (0x1U << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
#define HRTIM_OENR_TA2OEN_Pos (1U)
#define HRTIM_OENR_TA2OEN_Msk (0x1U << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
#define HRTIM_OENR_TB1OEN_Pos (2U)
#define HRTIM_OENR_TB1OEN_Msk (0x1U << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
#define HRTIM_OENR_TB2OEN_Pos (3U)
#define HRTIM_OENR_TB2OEN_Msk (0x1U << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
#define HRTIM_OENR_TC1OEN_Pos (4U)
#define HRTIM_OENR_TC1OEN_Msk (0x1U << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
#define HRTIM_OENR_TC2OEN_Pos (5U)
#define HRTIM_OENR_TC2OEN_Msk (0x1U << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
#define HRTIM_OENR_TD1OEN_Pos (6U)
#define HRTIM_OENR_TD1OEN_Msk (0x1U << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
#define HRTIM_OENR_TD2OEN_Pos (7U)
#define HRTIM_OENR_TD2OEN_Msk (0x1U << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
#define HRTIM_OENR_TE1OEN_Pos (8U)
#define HRTIM_OENR_TE1OEN_Msk (0x1U << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
#define HRTIM_OENR_TE2OEN_Pos (9U)
#define HRTIM_OENR_TE2OEN_Msk (0x1U << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
/**** Bit definition for Common HRTIM Timer output disable register ***********/
#define HRTIM_ODISR_TA1ODIS_Pos (0U)
#define HRTIM_ODISR_TA1ODIS_Msk (0x1U << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
#define HRTIM_ODISR_TA2ODIS_Pos (1U)
#define HRTIM_ODISR_TA2ODIS_Msk (0x1U << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
#define HRTIM_ODISR_TB1ODIS_Pos (2U)
#define HRTIM_ODISR_TB1ODIS_Msk (0x1U << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
#define HRTIM_ODISR_TB2ODIS_Pos (3U)
#define HRTIM_ODISR_TB2ODIS_Msk (0x1U << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
#define HRTIM_ODISR_TC1ODIS_Pos (4U)
#define HRTIM_ODISR_TC1ODIS_Msk (0x1U << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
#define HRTIM_ODISR_TC2ODIS_Pos (5U)
#define HRTIM_ODISR_TC2ODIS_Msk (0x1U << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
#define HRTIM_ODISR_TD1ODIS_Pos (6U)
#define HRTIM_ODISR_TD1ODIS_Msk (0x1U << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
#define HRTIM_ODISR_TD2ODIS_Pos (7U)
#define HRTIM_ODISR_TD2ODIS_Msk (0x1U << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
#define HRTIM_ODISR_TE1ODIS_Pos (8U)
#define HRTIM_ODISR_TE1ODIS_Msk (0x1U << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
#define HRTIM_ODISR_TE2ODIS_Pos (9U)
#define HRTIM_ODISR_TE2ODIS_Msk (0x1U << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
/**** Bit definition for Common HRTIM Timer output disable status register *****/
#define HRTIM_ODSR_TA1ODS_Pos (0U)
#define HRTIM_ODSR_TA1ODS_Msk (0x1U << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
#define HRTIM_ODSR_TA2ODS_Pos (1U)
#define HRTIM_ODSR_TA2ODS_Msk (0x1U << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
#define HRTIM_ODSR_TB1ODS_Pos (2U)
#define HRTIM_ODSR_TB1ODS_Msk (0x1U << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
#define HRTIM_ODSR_TB2ODS_Pos (3U)
#define HRTIM_ODSR_TB2ODS_Msk (0x1U << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
#define HRTIM_ODSR_TC1ODS_Pos (4U)
#define HRTIM_ODSR_TC1ODS_Msk (0x1U << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
#define HRTIM_ODSR_TC2ODS_Pos (5U)
#define HRTIM_ODSR_TC2ODS_Msk (0x1U << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
#define HRTIM_ODSR_TD1ODS_Pos (6U)
#define HRTIM_ODSR_TD1ODS_Msk (0x1U << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
#define HRTIM_ODSR_TD2ODS_Pos (7U)
#define HRTIM_ODSR_TD2ODS_Msk (0x1U << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
#define HRTIM_ODSR_TE1ODS_Pos (8U)
#define HRTIM_ODSR_TE1ODS_Msk (0x1U << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
#define HRTIM_ODSR_TE2ODS_Pos (9U)
#define HRTIM_ODSR_TE2ODS_Msk (0x1U << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1U << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1U << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
#define HRTIM_BMCR_BMCLK_Pos (2U)
#define HRTIM_BMCR_BMCLK_Msk (0xFU << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
#define HRTIM_BMCR_BMCLK_0 (0x1U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
#define HRTIM_BMCR_BMCLK_1 (0x2U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
#define HRTIM_BMCR_BMCLK_2 (0x4U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
#define HRTIM_BMCR_BMCLK_3 (0x8U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
#define HRTIM_BMCR_BMPRSC_Pos (6U)
#define HRTIM_BMCR_BMPRSC_Msk (0xFU << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
#define HRTIM_BMCR_BMPRSC_0 (0x1U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
#define HRTIM_BMCR_BMPRSC_1 (0x2U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
#define HRTIM_BMCR_BMPRSC_2 (0x4U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
#define HRTIM_BMCR_BMPRSC_3 (0x8U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
#define HRTIM_BMCR_BMPREN_Pos (10U)
#define HRTIM_BMCR_BMPREN_Msk (0x1U << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
#define HRTIM_BMCR_MTBM_Pos (16U)
#define HRTIM_BMCR_MTBM_Msk (0x1U << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
#define HRTIM_BMCR_TABM_Pos (17U)
#define HRTIM_BMCR_TABM_Msk (0x1U << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
#define HRTIM_BMCR_TBBM_Pos (18U)
#define HRTIM_BMCR_TBBM_Msk (0x1U << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
#define HRTIM_BMCR_TCBM_Pos (19U)
#define HRTIM_BMCR_TCBM_Msk (0x1U << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
#define HRTIM_BMCR_TDBM_Pos (20U)
#define HRTIM_BMCR_TDBM_Msk (0x1U << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
#define HRTIM_BMCR_TEBM_Pos (21U)
#define HRTIM_BMCR_TEBM_Msk (0x1U << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
#define HRTIM_BMCR_BMSTAT_Pos (31U)
#define HRTIM_BMCR_BMSTAT_Msk (0x1U << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
#define HRTIM_BMTRGR_SW_Pos (0U)
#define HRTIM_BMTRGR_SW_Msk (0x1U << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
#define HRTIM_BMTRGR_MSTRST_Pos (1U)
#define HRTIM_BMTRGR_MSTRST_Msk (0x1U << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
#define HRTIM_BMTRGR_MSTREP_Pos (2U)
#define HRTIM_BMTRGR_MSTREP_Msk (0x1U << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1U << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1U << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1U << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1U << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_BMTRGR_TARST_Pos (7U)
#define HRTIM_BMTRGR_TARST_Msk (0x1U << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
#define HRTIM_BMTRGR_TAREP_Pos (8U)
#define HRTIM_BMTRGR_TAREP_Msk (0x1U << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
#define HRTIM_BMTRGR_TACMP1_Pos (9U)
#define HRTIM_BMTRGR_TACMP1_Msk (0x1U << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_BMTRGR_TACMP2_Pos (10U)
#define HRTIM_BMTRGR_TACMP2_Msk (0x1U << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_BMTRGR_TBRST_Pos (11U)
#define HRTIM_BMTRGR_TBRST_Msk (0x1U << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
#define HRTIM_BMTRGR_TBREP_Pos (12U)
#define HRTIM_BMTRGR_TBREP_Msk (0x1U << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
#define HRTIM_BMTRGR_TBCMP1_Msk (0x1U << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
#define HRTIM_BMTRGR_TBCMP2_Msk (0x1U << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_BMTRGR_TCRST_Pos (15U)
#define HRTIM_BMTRGR_TCRST_Msk (0x1U << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
#define HRTIM_BMTRGR_TCREP_Pos (16U)
#define HRTIM_BMTRGR_TCREP_Msk (0x1U << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
#define HRTIM_BMTRGR_TCCMP1_Msk (0x1U << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_BMTRGR_TCCMP2_Pos (18U)
#define HRTIM_BMTRGR_TCCMP2_Msk (0x1U << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_BMTRGR_TDRST_Pos (19U)
#define HRTIM_BMTRGR_TDRST_Msk (0x1U << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
#define HRTIM_BMTRGR_TDREP_Pos (20U)
#define HRTIM_BMTRGR_TDREP_Msk (0x1U << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
#define HRTIM_BMTRGR_TDCMP1_Pos (21U)
#define HRTIM_BMTRGR_TDCMP1_Msk (0x1U << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
#define HRTIM_BMTRGR_TDCMP2_Msk (0x1U << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_BMTRGR_TERST_Pos (23U)
#define HRTIM_BMTRGR_TERST_Msk (0x1U << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
#define HRTIM_BMTRGR_TEREP_Pos (24U)
#define HRTIM_BMTRGR_TEREP_Msk (0x1U << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
#define HRTIM_BMTRGR_TECMP1_Pos (25U)
#define HRTIM_BMTRGR_TECMP1_Msk (0x1U << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_BMTRGR_TECMP2_Pos (26U)
#define HRTIM_BMTRGR_TECMP2_Msk (0x1U << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
#define HRTIM_BMTRGR_TAEEV7_Msk (0x1U << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
#define HRTIM_BMTRGR_TDEEV8_Msk (0x1U << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
#define HRTIM_BMTRGR_EEV7_Pos (29U)
#define HRTIM_BMTRGR_EEV7_Msk (0x1U << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
#define HRTIM_BMTRGR_EEV8_Pos (30U)
#define HRTIM_BMTRGR_EEV8_Msk (0x1U << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
#define HRTIM_BMTRGR_OCHPEV_Msk (0x1U << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
/******************* Bit definition for HRTIM_BMCMPR register ***************/
#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFU << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
/******************* Bit definition for HRTIM_BMPER register ****************/
#define HRTIM_BMPER_BMPER_Pos (0U)
#define HRTIM_BMPER_BMPER_Msk (0xFFFFU << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
/******************* Bit definition for HRTIM_EECR1 register ****************/
#define HRTIM_EECR1_EE1SRC_Pos (0U)
#define HRTIM_EECR1_EE1SRC_Msk (0x3U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
#define HRTIM_EECR1_EE1SRC_0 (0x1U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
#define HRTIM_EECR1_EE1SRC_1 (0x2U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
#define HRTIM_EECR1_EE1POL_Pos (2U)
#define HRTIM_EECR1_EE1POL_Msk (0x1U << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
#define HRTIM_EECR1_EE1SNS_Pos (3U)
#define HRTIM_EECR1_EE1SNS_Msk (0x3U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
#define HRTIM_EECR1_EE1SNS_0 (0x1U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
#define HRTIM_EECR1_EE1SNS_1 (0x2U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
#define HRTIM_EECR1_EE1FAST_Pos (5U)
#define HRTIM_EECR1_EE1FAST_Msk (0x1U << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
#define HRTIM_EECR1_EE2SRC_Pos (6U)
#define HRTIM_EECR1_EE2SRC_Msk (0x3U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
#define HRTIM_EECR1_EE2SRC_0 (0x1U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
#define HRTIM_EECR1_EE2SRC_1 (0x2U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
#define HRTIM_EECR1_EE2POL_Pos (8U)
#define HRTIM_EECR1_EE2POL_Msk (0x1U << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
#define HRTIM_EECR1_EE2SNS_Pos (9U)
#define HRTIM_EECR1_EE2SNS_Msk (0x3U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
#define HRTIM_EECR1_EE2SNS_0 (0x1U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
#define HRTIM_EECR1_EE2SNS_1 (0x2U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
#define HRTIM_EECR1_EE2FAST_Pos (11U)
#define HRTIM_EECR1_EE2FAST_Msk (0x1U << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
#define HRTIM_EECR1_EE3SRC_Pos (12U)
#define HRTIM_EECR1_EE3SRC_Msk (0x3U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
#define HRTIM_EECR1_EE3SRC_0 (0x1U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
#define HRTIM_EECR1_EE3SRC_1 (0x2U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
#define HRTIM_EECR1_EE3POL_Pos (14U)
#define HRTIM_EECR1_EE3POL_Msk (0x1U << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
#define HRTIM_EECR1_EE3SNS_Pos (15U)
#define HRTIM_EECR1_EE3SNS_Msk (0x3U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
#define HRTIM_EECR1_EE3SNS_0 (0x1U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
#define HRTIM_EECR1_EE3SNS_1 (0x2U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
#define HRTIM_EECR1_EE3FAST_Pos (17U)
#define HRTIM_EECR1_EE3FAST_Msk (0x1U << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
#define HRTIM_EECR1_EE4SRC_Pos (18U)
#define HRTIM_EECR1_EE4SRC_Msk (0x3U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
#define HRTIM_EECR1_EE4SRC_0 (0x1U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
#define HRTIM_EECR1_EE4SRC_1 (0x2U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
#define HRTIM_EECR1_EE4POL_Pos (20U)
#define HRTIM_EECR1_EE4POL_Msk (0x1U << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
#define HRTIM_EECR1_EE4SNS_Pos (21U)
#define HRTIM_EECR1_EE4SNS_Msk (0x3U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
#define HRTIM_EECR1_EE4SNS_0 (0x1U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
#define HRTIM_EECR1_EE4SNS_1 (0x2U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
#define HRTIM_EECR1_EE4FAST_Pos (23U)
#define HRTIM_EECR1_EE4FAST_Msk (0x1U << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
#define HRTIM_EECR1_EE5SRC_Pos (24U)
#define HRTIM_EECR1_EE5SRC_Msk (0x3U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
#define HRTIM_EECR1_EE5SRC_0 (0x1U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
#define HRTIM_EECR1_EE5SRC_1 (0x2U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
#define HRTIM_EECR1_EE5POL_Pos (26U)
#define HRTIM_EECR1_EE5POL_Msk (0x1U << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
#define HRTIM_EECR1_EE5SNS_Pos (27U)
#define HRTIM_EECR1_EE5SNS_Msk (0x3U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
#define HRTIM_EECR1_EE5SNS_0 (0x1U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
#define HRTIM_EECR1_EE5SNS_1 (0x2U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
#define HRTIM_EECR1_EE5FAST_Pos (29U)
#define HRTIM_EECR1_EE5FAST_Msk (0x1U << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
/******************* Bit definition for HRTIM_EECR2 register ****************/
#define HRTIM_EECR2_EE6SRC_Pos (0U)
#define HRTIM_EECR2_EE6SRC_Msk (0x3U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
#define HRTIM_EECR2_EE6SRC_0 (0x1U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
#define HRTIM_EECR2_EE6SRC_1 (0x2U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
#define HRTIM_EECR2_EE6POL_Pos (2U)
#define HRTIM_EECR2_EE6POL_Msk (0x1U << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
#define HRTIM_EECR2_EE6SNS_Pos (3U)
#define HRTIM_EECR2_EE6SNS_Msk (0x3U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
#define HRTIM_EECR2_EE6SNS_0 (0x1U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
#define HRTIM_EECR2_EE6SNS_1 (0x2U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
#define HRTIM_EECR2_EE7SRC_Pos (6U)
#define HRTIM_EECR2_EE7SRC_Msk (0x3U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
#define HRTIM_EECR2_EE7SRC_0 (0x1U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
#define HRTIM_EECR2_EE7SRC_1 (0x2U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
#define HRTIM_EECR2_EE7POL_Pos (8U)
#define HRTIM_EECR2_EE7POL_Msk (0x1U << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
#define HRTIM_EECR2_EE7SNS_Pos (9U)
#define HRTIM_EECR2_EE7SNS_Msk (0x3U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
#define HRTIM_EECR2_EE7SNS_0 (0x1U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
#define HRTIM_EECR2_EE7SNS_1 (0x2U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
#define HRTIM_EECR2_EE8SRC_Pos (12U)
#define HRTIM_EECR2_EE8SRC_Msk (0x3U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
#define HRTIM_EECR2_EE8SRC_0 (0x1U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
#define HRTIM_EECR2_EE8SRC_1 (0x2U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
#define HRTIM_EECR2_EE8POL_Pos (14U)
#define HRTIM_EECR2_EE8POL_Msk (0x1U << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
#define HRTIM_EECR2_EE8SNS_Pos (15U)
#define HRTIM_EECR2_EE8SNS_Msk (0x3U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
#define HRTIM_EECR2_EE8SNS_0 (0x1U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
#define HRTIM_EECR2_EE8SNS_1 (0x2U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
#define HRTIM_EECR2_EE9SRC_Pos (18U)
#define HRTIM_EECR2_EE9SRC_Msk (0x3U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
#define HRTIM_EECR2_EE9SRC_0 (0x1U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
#define HRTIM_EECR2_EE9SRC_1 (0x2U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
#define HRTIM_EECR2_EE9POL_Pos (20U)
#define HRTIM_EECR2_EE9POL_Msk (0x1U << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
#define HRTIM_EECR2_EE9SNS_Pos (21U)
#define HRTIM_EECR2_EE9SNS_Msk (0x3U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
#define HRTIM_EECR2_EE9SNS_0 (0x1U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
#define HRTIM_EECR2_EE9SNS_1 (0x2U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
#define HRTIM_EECR2_EE10SRC_Pos (24U)
#define HRTIM_EECR2_EE10SRC_Msk (0x3U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
#define HRTIM_EECR2_EE10SRC_0 (0x1U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
#define HRTIM_EECR2_EE10SRC_1 (0x2U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
#define HRTIM_EECR2_EE10POL_Pos (26U)
#define HRTIM_EECR2_EE10POL_Msk (0x1U << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
#define HRTIM_EECR2_EE10SNS_Pos (27U)
#define HRTIM_EECR2_EE10SNS_Msk (0x3U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
#define HRTIM_EECR2_EE10SNS_0 (0x1U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
#define HRTIM_EECR2_EE10SNS_1 (0x2U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
/******************* Bit definition for HRTIM_EECR3 register ****************/
#define HRTIM_EECR3_EE6F_Pos (0U)
#define HRTIM_EECR3_EE6F_Msk (0xFU << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
#define HRTIM_EECR3_EE6F_0 (0x1U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
#define HRTIM_EECR3_EE6F_1 (0x2U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
#define HRTIM_EECR3_EE6F_2 (0x4U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
#define HRTIM_EECR3_EE6F_3 (0x8U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
#define HRTIM_EECR3_EE7F_Pos (6U)
#define HRTIM_EECR3_EE7F_Msk (0xFU << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
#define HRTIM_EECR3_EE7F_0 (0x1U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
#define HRTIM_EECR3_EE7F_1 (0x2U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
#define HRTIM_EECR3_EE7F_2 (0x4U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
#define HRTIM_EECR3_EE7F_3 (0x8U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
#define HRTIM_EECR3_EE8F_Pos (12U)
#define HRTIM_EECR3_EE8F_Msk (0xFU << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
#define HRTIM_EECR3_EE8F_0 (0x1U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
#define HRTIM_EECR3_EE8F_1 (0x2U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
#define HRTIM_EECR3_EE8F_2 (0x4U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
#define HRTIM_EECR3_EE8F_3 (0x8U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
#define HRTIM_EECR3_EE9F_Pos (18U)
#define HRTIM_EECR3_EE9F_Msk (0xFU << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
#define HRTIM_EECR3_EE9F_0 (0x1U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
#define HRTIM_EECR3_EE9F_1 (0x2U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
#define HRTIM_EECR3_EE9F_2 (0x4U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
#define HRTIM_EECR3_EE9F_3 (0x8U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
#define HRTIM_EECR3_EE10F_Pos (24U)
#define HRTIM_EECR3_EE10F_Msk (0xFU << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
#define HRTIM_EECR3_EE10F_0 (0x1U << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
#define HRTIM_EECR3_EE10F_1 (0x2U << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
#define HRTIM_EECR3_EE10F_2 (0x4U << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
#define HRTIM_EECR3_EE10F_3 (0x8U << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
#define HRTIM_EECR3_EEVSD_Pos (30U)
#define HRTIM_EECR3_EEVSD_Msk (0x3U << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
#define HRTIM_EECR3_EEVSD_0 (0x1U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
#define HRTIM_EECR3_EEVSD_1 (0x2U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
/******************* Bit definition for HRTIM_ADC1R register ****************/
#define HRTIM_ADC1R_AD1MC1_Pos (0U)
#define HRTIM_ADC1R_AD1MC1_Msk (0x1U << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
#define HRTIM_ADC1R_AD1MC2_Pos (1U)
#define HRTIM_ADC1R_AD1MC2_Msk (0x1U << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
#define HRTIM_ADC1R_AD1MC3_Pos (2U)
#define HRTIM_ADC1R_AD1MC3_Msk (0x1U << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
#define HRTIM_ADC1R_AD1MC4_Pos (3U)
#define HRTIM_ADC1R_AD1MC4_Msk (0x1U << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
#define HRTIM_ADC1R_AD1MPER_Pos (4U)
#define HRTIM_ADC1R_AD1MPER_Msk (0x1U << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
#define HRTIM_ADC1R_AD1EEV1_Msk (0x1U << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
#define HRTIM_ADC1R_AD1EEV2_Msk (0x1U << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
#define HRTIM_ADC1R_AD1EEV3_Msk (0x1U << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
#define HRTIM_ADC1R_AD1EEV4_Msk (0x1U << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
#define HRTIM_ADC1R_AD1EEV5_Msk (0x1U << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
#define HRTIM_ADC1R_AD1TAC2_Pos (10U)
#define HRTIM_ADC1R_AD1TAC2_Msk (0x1U << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
#define HRTIM_ADC1R_AD1TAC3_Msk (0x1U << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
#define HRTIM_ADC1R_AD1TAC4_Msk (0x1U << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
#define HRTIM_ADC1R_AD1TAPER_Msk (0x1U << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
#define HRTIM_ADC1R_AD1TARST_Pos (14U)
#define HRTIM_ADC1R_AD1TARST_Msk (0x1U << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
#define HRTIM_ADC1R_AD1TBC2_Pos (15U)
#define HRTIM_ADC1R_AD1TBC2_Msk (0x1U << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
#define HRTIM_ADC1R_AD1TBC3_Msk (0x1U << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
#define HRTIM_ADC1R_AD1TBC4_Msk (0x1U << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
#define HRTIM_ADC1R_AD1TBPER_Msk (0x1U << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
#define HRTIM_ADC1R_AD1TBRST_Msk (0x1U << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
#define HRTIM_ADC1R_AD1TCC2_Pos (20U)
#define HRTIM_ADC1R_AD1TCC2_Msk (0x1U << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
#define HRTIM_ADC1R_AD1TCC3_Msk (0x1U << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
#define HRTIM_ADC1R_AD1TCC4_Msk (0x1U << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
#define HRTIM_ADC1R_AD1TCPER_Msk (0x1U << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
#define HRTIM_ADC1R_AD1TDC2_Pos (24U)
#define HRTIM_ADC1R_AD1TDC2_Msk (0x1U << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
#define HRTIM_ADC1R_AD1TDC3_Msk (0x1U << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
#define HRTIM_ADC1R_AD1TDC4_Msk (0x1U << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
#define HRTIM_ADC1R_AD1TDPER_Msk (0x1U << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
#define HRTIM_ADC1R_AD1TEC2_Pos (28U)
#define HRTIM_ADC1R_AD1TEC2_Msk (0x1U << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
#define HRTIM_ADC1R_AD1TEC3_Msk (0x1U << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
#define HRTIM_ADC1R_AD1TEC4_Msk (0x1U << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
#define HRTIM_ADC1R_AD1TEPER_Msk (0x1U << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
/******************* Bit definition for HRTIM_ADC2R register ****************/
#define HRTIM_ADC2R_AD2MC1_Pos (0U)
#define HRTIM_ADC2R_AD2MC1_Msk (0x1U << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
#define HRTIM_ADC2R_AD2MC2_Pos (1U)
#define HRTIM_ADC2R_AD2MC2_Msk (0x1U << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
#define HRTIM_ADC2R_AD2MC3_Pos (2U)
#define HRTIM_ADC2R_AD2MC3_Msk (0x1U << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
#define HRTIM_ADC2R_AD2MC4_Pos (3U)
#define HRTIM_ADC2R_AD2MC4_Msk (0x1U << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
#define HRTIM_ADC2R_AD2MPER_Pos (4U)
#define HRTIM_ADC2R_AD2MPER_Msk (0x1U << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
#define HRTIM_ADC2R_AD2EEV6_Msk (0x1U << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
#define HRTIM_ADC2R_AD2EEV7_Msk (0x1U << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
#define HRTIM_ADC2R_AD2EEV8_Msk (0x1U << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
#define HRTIM_ADC2R_AD2EEV9_Msk (0x1U << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
#define HRTIM_ADC2R_AD2EEV10_Msk (0x1U << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
#define HRTIM_ADC2R_AD2TAC2_Msk (0x1U << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
#define HRTIM_ADC2R_AD2TAC3_Pos (11U)
#define HRTIM_ADC2R_AD2TAC3_Msk (0x1U << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
#define HRTIM_ADC2R_AD2TAC4_Msk (0x1U << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
#define HRTIM_ADC2R_AD2TAPER_Msk (0x1U << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
#define HRTIM_ADC2R_AD2TBC2_Msk (0x1U << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
#define HRTIM_ADC2R_AD2TBC3_Pos (15U)
#define HRTIM_ADC2R_AD2TBC3_Msk (0x1U << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
#define HRTIM_ADC2R_AD2TBC4_Msk (0x1U << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
#define HRTIM_ADC2R_AD2TBPER_Msk (0x1U << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
#define HRTIM_ADC2R_AD2TCC2_Msk (0x1U << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
#define HRTIM_ADC2R_AD2TCC3_Pos (19U)
#define HRTIM_ADC2R_AD2TCC3_Msk (0x1U << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
#define HRTIM_ADC2R_AD2TCC4_Msk (0x1U << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
#define HRTIM_ADC2R_AD2TCPER_Msk (0x1U << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
#define HRTIM_ADC2R_AD2TCRST_Msk (0x1U << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
#define HRTIM_ADC2R_AD2TDC2_Msk (0x1U << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
#define HRTIM_ADC2R_AD2TDC3_Pos (24U)
#define HRTIM_ADC2R_AD2TDC3_Msk (0x1U << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
#define HRTIM_ADC2R_AD2TDC4_Msk (0x1U << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
#define HRTIM_ADC2R_AD2TDPER_Msk (0x1U << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
#define HRTIM_ADC2R_AD2TDRST_Msk (0x1U << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
#define HRTIM_ADC2R_AD2TEC2_Msk (0x1U << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
#define HRTIM_ADC2R_AD2TEC3_Msk (0x1U << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
#define HRTIM_ADC2R_AD2TEC4_Msk (0x1U << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
#define HRTIM_ADC2R_AD2TERST_Pos (31U)
#define HRTIM_ADC2R_AD2TERST_Msk (0x1U << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
/******************* Bit definition for HRTIM_ADC3R register ****************/
#define HRTIM_ADC3R_AD3MC1_Pos (0U)
#define HRTIM_ADC3R_AD3MC1_Msk (0x1U << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
#define HRTIM_ADC3R_AD3MC2_Pos (1U)
#define HRTIM_ADC3R_AD3MC2_Msk (0x1U << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
#define HRTIM_ADC3R_AD3MC3_Pos (2U)
#define HRTIM_ADC3R_AD3MC3_Msk (0x1U << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
#define HRTIM_ADC3R_AD3MC4_Pos (3U)
#define HRTIM_ADC3R_AD3MC4_Msk (0x1U << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
#define HRTIM_ADC3R_AD3MPER_Pos (4U)
#define HRTIM_ADC3R_AD3MPER_Msk (0x1U << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
#define HRTIM_ADC3R_AD3EEV1_Msk (0x1U << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
#define HRTIM_ADC3R_AD3EEV2_Msk (0x1U << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
#define HRTIM_ADC3R_AD3EEV3_Msk (0x1U << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
#define HRTIM_ADC3R_AD3EEV4_Msk (0x1U << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
#define HRTIM_ADC3R_AD3EEV5_Msk (0x1U << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
#define HRTIM_ADC3R_AD3TAC2_Pos (10U)
#define HRTIM_ADC3R_AD3TAC2_Msk (0x1U << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
#define HRTIM_ADC3R_AD3TAC3_Msk (0x1U << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
#define HRTIM_ADC3R_AD3TAC4_Msk (0x1U << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
#define HRTIM_ADC3R_AD3TAPER_Msk (0x1U << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
#define HRTIM_ADC3R_AD3TARST_Pos (14U)
#define HRTIM_ADC3R_AD3TARST_Msk (0x1U << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
#define HRTIM_ADC3R_AD3TBC2_Pos (15U)
#define HRTIM_ADC3R_AD3TBC2_Msk (0x1U << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
#define HRTIM_ADC3R_AD3TBC3_Msk (0x1U << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
#define HRTIM_ADC3R_AD3TBC4_Msk (0x1U << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
#define HRTIM_ADC3R_AD3TBPER_Msk (0x1U << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
#define HRTIM_ADC3R_AD3TBRST_Msk (0x1U << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
#define HRTIM_ADC3R_AD3TCC2_Pos (20U)
#define HRTIM_ADC3R_AD3TCC2_Msk (0x1U << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
#define HRTIM_ADC3R_AD3TCC3_Msk (0x1U << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
#define HRTIM_ADC3R_AD3TCC4_Msk (0x1U << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
#define HRTIM_ADC3R_AD3TCPER_Msk (0x1U << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
#define HRTIM_ADC3R_AD3TDC2_Pos (24U)
#define HRTIM_ADC3R_AD3TDC2_Msk (0x1U << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
#define HRTIM_ADC3R_AD3TDC3_Msk (0x1U << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
#define HRTIM_ADC3R_AD3TDC4_Msk (0x1U << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
#define HRTIM_ADC3R_AD3TDPER_Msk (0x1U << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
#define HRTIM_ADC3R_AD3TEC2_Pos (28U)
#define HRTIM_ADC3R_AD3TEC2_Msk (0x1U << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
#define HRTIM_ADC3R_AD3TEC3_Msk (0x1U << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
#define HRTIM_ADC3R_AD3TEC4_Msk (0x1U << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
#define HRTIM_ADC3R_AD3TEPER_Msk (0x1U << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
/******************* Bit definition for HRTIM_ADC4R register ****************/
#define HRTIM_ADC4R_AD4MC1_Pos (0U)
#define HRTIM_ADC4R_AD4MC1_Msk (0x1U << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
#define HRTIM_ADC4R_AD4MC2_Pos (1U)
#define HRTIM_ADC4R_AD4MC2_Msk (0x1U << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
#define HRTIM_ADC4R_AD4MC3_Pos (2U)
#define HRTIM_ADC4R_AD4MC3_Msk (0x1U << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
#define HRTIM_ADC4R_AD4MC4_Pos (3U)
#define HRTIM_ADC4R_AD4MC4_Msk (0x1U << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
#define HRTIM_ADC4R_AD4MPER_Pos (4U)
#define HRTIM_ADC4R_AD4MPER_Msk (0x1U << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
#define HRTIM_ADC4R_AD4EEV6_Msk (0x1U << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
#define HRTIM_ADC4R_AD4EEV7_Msk (0x1U << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
#define HRTIM_ADC4R_AD4EEV8_Msk (0x1U << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
#define HRTIM_ADC4R_AD4EEV9_Msk (0x1U << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
#define HRTIM_ADC4R_AD4EEV10_Msk (0x1U << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
#define HRTIM_ADC4R_AD4TAC2_Msk (0x1U << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
#define HRTIM_ADC4R_AD4TAC3_Pos (11U)
#define HRTIM_ADC4R_AD4TAC3_Msk (0x1U << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
#define HRTIM_ADC4R_AD4TAC4_Msk (0x1U << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
#define HRTIM_ADC4R_AD4TAPER_Msk (0x1U << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
#define HRTIM_ADC4R_AD4TBC2_Msk (0x1U << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
#define HRTIM_ADC4R_AD4TBC3_Pos (15U)
#define HRTIM_ADC4R_AD4TBC3_Msk (0x1U << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
#define HRTIM_ADC4R_AD4TBC4_Msk (0x1U << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
#define HRTIM_ADC4R_AD4TBPER_Msk (0x1U << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
#define HRTIM_ADC4R_AD4TCC2_Msk (0x1U << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
#define HRTIM_ADC4R_AD4TCC3_Pos (19U)
#define HRTIM_ADC4R_AD4TCC3_Msk (0x1U << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
#define HRTIM_ADC4R_AD4TCC4_Msk (0x1U << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
#define HRTIM_ADC4R_AD4TCPER_Msk (0x1U << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
#define HRTIM_ADC4R_AD4TCRST_Msk (0x1U << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
#define HRTIM_ADC4R_AD4TDC2_Msk (0x1U << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
#define HRTIM_ADC4R_AD4TDC3_Pos (24U)
#define HRTIM_ADC4R_AD4TDC3_Msk (0x1U << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
#define HRTIM_ADC4R_AD4TDC4_Msk (0x1U << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
#define HRTIM_ADC4R_AD4TDPER_Msk (0x1U << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
#define HRTIM_ADC4R_AD4TDRST_Msk (0x1U << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
#define HRTIM_ADC4R_AD4TEC2_Msk (0x1U << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
#define HRTIM_ADC4R_AD4TEC3_Msk (0x1U << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
#define HRTIM_ADC4R_AD4TEC4_Msk (0x1U << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
#define HRTIM_ADC4R_AD4TERST_Pos (31U)
#define HRTIM_ADC4R_AD4TERST_Msk (0x1U << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
/******************* Bit definition for HRTIM_FLTINR1 register ***************/
#define HRTIM_FLTINR1_FLT1E_Pos (0U)
#define HRTIM_FLTINR1_FLT1E_Msk (0x1U << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
#define HRTIM_FLTINR1_FLT1P_Pos (1U)
#define HRTIM_FLTINR1_FLT1P_Msk (0x1U << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1U << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
#define HRTIM_FLTINR1_FLT1F_Pos (3U)
#define HRTIM_FLTINR1_FLT1F_Msk (0xFU << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
#define HRTIM_FLTINR1_FLT1F_0 (0x1U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR1_FLT1F_1 (0x2U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR1_FLT1F_2 (0x4U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR1_FLT1F_3 (0x8U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1U << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
#define HRTIM_FLTINR1_FLT2E_Pos (8U)
#define HRTIM_FLTINR1_FLT2E_Msk (0x1U << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
#define HRTIM_FLTINR1_FLT2P_Pos (9U)
#define HRTIM_FLTINR1_FLT2P_Msk (0x1U << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1U << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
#define HRTIM_FLTINR1_FLT2F_Pos (11U)
#define HRTIM_FLTINR1_FLT2F_Msk (0xFU << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
#define HRTIM_FLTINR1_FLT2F_0 (0x1U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
#define HRTIM_FLTINR1_FLT2F_1 (0x2U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
#define HRTIM_FLTINR1_FLT2F_2 (0x4U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
#define HRTIM_FLTINR1_FLT2F_3 (0x8U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1U << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
#define HRTIM_FLTINR1_FLT3E_Pos (16U)
#define HRTIM_FLTINR1_FLT3E_Msk (0x1U << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
#define HRTIM_FLTINR1_FLT3P_Pos (17U)
#define HRTIM_FLTINR1_FLT3P_Msk (0x1U << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1U << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
#define HRTIM_FLTINR1_FLT3F_Pos (19U)
#define HRTIM_FLTINR1_FLT3F_Msk (0xFU << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
#define HRTIM_FLTINR1_FLT3F_0 (0x1U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
#define HRTIM_FLTINR1_FLT3F_1 (0x2U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
#define HRTIM_FLTINR1_FLT3F_2 (0x4U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
#define HRTIM_FLTINR1_FLT3F_3 (0x8U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1U << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
#define HRTIM_FLTINR1_FLT4E_Pos (24U)
#define HRTIM_FLTINR1_FLT4E_Msk (0x1U << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
#define HRTIM_FLTINR1_FLT4P_Pos (25U)
#define HRTIM_FLTINR1_FLT4P_Msk (0x1U << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1U << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
#define HRTIM_FLTINR1_FLT4F_Pos (27U)
#define HRTIM_FLTINR1_FLT4F_Msk (0xFU << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
#define HRTIM_FLTINR1_FLT4F_0 (0x1U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
#define HRTIM_FLTINR1_FLT4F_1 (0x2U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
#define HRTIM_FLTINR1_FLT4F_2 (0x4U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
#define HRTIM_FLTINR1_FLT4F_3 (0x8U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1U << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
/******************* Bit definition for HRTIM_FLTINR2 register ***************/
#define HRTIM_FLTINR2_FLT5E_Pos (0U)
#define HRTIM_FLTINR2_FLT5E_Msk (0x1U << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
#define HRTIM_FLTINR2_FLT5P_Pos (1U)
#define HRTIM_FLTINR2_FLT5P_Msk (0x1U << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1U << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
#define HRTIM_FLTINR2_FLT5F_Pos (3U)
#define HRTIM_FLTINR2_FLT5F_Msk (0xFU << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
#define HRTIM_FLTINR2_FLT5F_0 (0x1U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR2_FLT5F_1 (0x2U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR2_FLT5F_2 (0x4U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR2_FLT5F_3 (0x8U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1U << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
#define HRTIM_FLTINR2_FLTSD_Pos (24U)
#define HRTIM_FLTINR2_FLTSD_Msk (0x3U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
#define HRTIM_FLTINR2_FLTSD_0 (0x1U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
#define HRTIM_FLTINR2_FLTSD_1 (0x2U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
/******************* Bit definition for HRTIM_BDMUPR register ***************/
#define HRTIM_BDMUPR_MCR_Pos (0U)
#define HRTIM_BDMUPR_MCR_Msk (0x1U << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
#define HRTIM_BDMUPR_MICR_Pos (1U)
#define HRTIM_BDMUPR_MICR_Msk (0x1U << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
#define HRTIM_BDMUPR_MDIER_Pos (2U)
#define HRTIM_BDMUPR_MDIER_Msk (0x1U << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
#define HRTIM_BDMUPR_MCNT_Pos (3U)
#define HRTIM_BDMUPR_MCNT_Msk (0x1U << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
#define HRTIM_BDMUPR_MPER_Pos (4U)
#define HRTIM_BDMUPR_MPER_Msk (0x1U << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
#define HRTIM_BDMUPR_MREP_Pos (5U)
#define HRTIM_BDMUPR_MREP_Msk (0x1U << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
#define HRTIM_BDMUPR_MCMP1_Pos (6U)
#define HRTIM_BDMUPR_MCMP1_Msk (0x1U << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
#define HRTIM_BDMUPR_MCMP2_Pos (7U)
#define HRTIM_BDMUPR_MCMP2_Msk (0x1U << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
#define HRTIM_BDMUPR_MCMP3_Pos (8U)
#define HRTIM_BDMUPR_MCMP3_Msk (0x1U << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
#define HRTIM_BDMUPR_MCMP4_Pos (9U)
#define HRTIM_BDMUPR_MCMP4_Msk (0x1U << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
/******************* Bit definition for HRTIM_BDTUPR register ***************/
#define HRTIM_BDTUPR_TIMCR_Pos (0U)
#define HRTIM_BDTUPR_TIMCR_Msk (0x1U << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
#define HRTIM_BDTUPR_TIMICR_Pos (1U)
#define HRTIM_BDTUPR_TIMICR_Msk (0x1U << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
#define HRTIM_BDTUPR_TIMDIER_Msk (0x1U << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
#define HRTIM_BDTUPR_TIMCNT_Msk (0x1U << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
#define HRTIM_BDTUPR_TIMPER_Pos (4U)
#define HRTIM_BDTUPR_TIMPER_Msk (0x1U << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
#define HRTIM_BDTUPR_TIMREP_Pos (5U)
#define HRTIM_BDTUPR_TIMREP_Msk (0x1U << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1U << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1U << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1U << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1U << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
#define HRTIM_BDTUPR_TIMDTR_Msk (0x1U << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1U << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1U << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1U << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1U << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1U << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1U << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1U << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1U << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
/******************* Bit definition for HRTIM_BDMADR register ***************/
#define HRTIM_BDMADR_BDMADR_Pos (0U)
#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFU << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
/******************************************************************************/
/* */
/* MDIOS */
/* */
/******************************************************************************/
/******************** Bit definition for MDIOS_CR register *******************/
#define MDIOS_CR_EN_Pos (0U)
#define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
#define MDIOS_CR_WRIE_Pos (1U)
#define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
#define MDIOS_CR_RDIE_Pos (2U)
#define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
#define MDIOS_CR_EIE_Pos (3U)
#define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
#define MDIOS_CR_DPC_Pos (7U)
#define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
#define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
#define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
#define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
#define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
#define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
/******************** Bit definition for MDIOS_SR register *******************/
#define MDIOS_SR_PERF_Pos (0U)
#define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
#define MDIOS_SR_SERF_Pos (1U)
#define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
#define MDIOS_SR_TERF_Pos (2U)
#define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
/******************** Bit definition for MDIOS_CLRFR register *******************/
#define MDIOS_SR_CPERF_Pos (0U)
#define MDIOS_SR_CPERF_Msk (0x1U << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
#define MDIOS_SR_CSERF_Pos (1U)
#define MDIOS_SR_CSERF_Msk (0x1U << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
#define MDIOS_SR_CTERF_Pos (2U)
#define MDIOS_SR_CTERF_Msk (0x1U << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
/******************************************************************************/
/* */
/* USB_OTG */
/* */
/******************************************************************************/
/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
/******************** Bit definition forUSB_OTG_HCFG register ********************/
#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
#define USB_OTG_HCFG_FSLSS_Pos (2U)
#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
/******************** Bit definition forUSB_OTG_DCFG register ********************/
#define USB_OTG_DCFG_DSPD_Pos (0U)
#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
#define USB_OTG_DCFG_DAD_Pos (4U)
#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
#define USB_OTG_DCFG_PFIVL_Pos (11U)
#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
/******************** Bit definition forUSB_OTG_PCGCR register ********************/
#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
#define USB_OTG_GOTGINT_SEDET_Pos (2U)
#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
/******************** Bit definition forUSB_OTG_DCTL register ********************/
#define USB_OTG_DCTL_RWUSIG_Pos (0U)
#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
#define USB_OTG_DCTL_SDIS_Pos (1U)
#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
#define USB_OTG_DCTL_GINSTS_Pos (2U)
#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
#define USB_OTG_DCTL_GONSTS_Pos (3U)
#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
#define USB_OTG_DCTL_TCTL_Pos (4U)
#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
#define USB_OTG_DCTL_SGINAK_Pos (7U)
#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
#define USB_OTG_DCTL_CGINAK_Pos (8U)
#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
#define USB_OTG_DCTL_SGONAK_Pos (9U)
#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
#define USB_OTG_DCTL_CGONAK_Pos (10U)
#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
/******************** Bit definition forUSB_OTG_HFIR register ********************/
#define USB_OTG_HFIR_FRIVL_Pos (0U)
#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
/******************** Bit definition forUSB_OTG_HFNUM register ********************/
#define USB_OTG_HFNUM_FRNUM_Pos (0U)
#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
#define USB_OTG_HFNUM_FTREM_Pos (16U)
#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
/******************** Bit definition forUSB_OTG_DSTS register ********************/
#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
#define USB_OTG_DSTS_EERR_Pos (3U)
#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
#define USB_OTG_DSTS_FNSOF_Pos (8U)
#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
#define USB_OTG_GAHBCFG_GINT_Pos (0U)
#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPMSK_TOM_Pos (3U)
#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPMSK_BIM_Pos (9U)
#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
/******************** Bit definition forUSB_OTG_HAINT register ********************/
#define USB_OTG_HAINT_HAINT_Pos (0U)
#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
#define USB_OTG_GINTSTS_MMIS_Pos (1U)
#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
#define USB_OTG_GINTSTS_SOF_Pos (3U)
#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
#define USB_OTG_GINTSTS_USBRST_Pos (12U)
#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
#define USB_OTG_GINTSTS_EOPF_Pos (15U)
#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
#define USB_OTG_GINTSTS_HCINT_Pos (25U)
#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
#define USB_OTG_GINTMSK_MMISM_Pos (1U)
#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
#define USB_OTG_GINTMSK_SOFM_Pos (3U)
#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
#define USB_OTG_GINTMSK_USBRST_Pos (12U)
#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
#define USB_OTG_GINTMSK_HCIM_Pos (25U)
#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
#define USB_OTG_GINTMSK_WUIM_Pos (31U)
#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
/******************** Bit definition forUSB_OTG_DAINT register ********************/
#define USB_OTG_DAINT_IEPINT_Pos (0U)
#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
#define USB_OTG_DAINT_OEPINT_Pos (16U)
#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_DPID_Pos (15U)
#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_NPTXFSA_Pos (0U)
#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
#define USB_OTG_NPTXFD_Pos (16U)
#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
#define USB_OTG_TX0FSA_Pos (0U)
#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
#define USB_OTG_TX0FD_Pos (16U)
#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
/******************** Bit definition forUSB_OTG_GCCFG register ********************/
#define USB_OTG_GCCFG_DCDET_Pos (0U)
#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
#define USB_OTG_GCCFG_PDET_Pos (1U)
#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
#define USB_OTG_GCCFG_SDET_Pos (2U)
#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
#define USB_OTG_GCCFG_PS2DET_Pos (3U)
#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
#define USB_OTG_GCCFG_BCDEN_Pos (17U)
#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
#define USB_OTG_GCCFG_DCDEN_Pos (18U)
#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
#define USB_OTG_GCCFG_PDEN_Pos (19U)
#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
#define USB_OTG_GCCFG_SDEN_Pos (20U)
#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
#define USB_OTG_GCCFG_VBDEN_Pos (21U)
#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
#define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
/******************** Bit definition forUSB_OTG_CID register ********************/
#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
#define USB_OTG_GLPMCFG_BESL_Pos (2U)
#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
/******************** Bit definition forUSB_OTG_HPRT register ********************/
#define USB_OTG_HPRT_PCSTS_Pos (0U)
#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
#define USB_OTG_HPRT_PCDET_Pos (1U)
#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
#define USB_OTG_HPRT_PENA_Pos (2U)
#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
#define USB_OTG_HPRT_PENCHNG_Pos (3U)
#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
#define USB_OTG_HPRT_POCA_Pos (4U)
#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
#define USB_OTG_HPRT_POCCHNG_Pos (5U)
#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
#define USB_OTG_HPRT_PRES_Pos (6U)
#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
#define USB_OTG_HPRT_PSUSP_Pos (7U)
#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
#define USB_OTG_HPRT_PRST_Pos (8U)
#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
#define USB_OTG_HPRT_PLSTS_Pos (10U)
#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_HPRT_PPWR_Pos (12U)
#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
#define USB_OTG_HPRT_PTCTL_Pos (13U)
#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
#define USB_OTG_HPRT_PSPD_Pos (17U)
#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DIEPCTL_STALL_Pos (21U)
#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_HCCHAR_MC_Pos (20U)
#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
#define USB_OTG_HCCHAR_DAD_Pos (22U)
#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
#define USB_OTG_HCCHAR_CHENA_Pos (31U)
#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
/******************** Bit definition forUSB_OTG_HCINT register ********************/
#define USB_OTG_HCINT_XFRC_Pos (0U)
#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
#define USB_OTG_HCINT_CHH_Pos (1U)
#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
#define USB_OTG_HCINT_AHBERR_Pos (2U)
#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINT_STALL_Pos (3U)
#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
#define USB_OTG_HCINT_NAK_Pos (4U)
#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
#define USB_OTG_HCINT_ACK_Pos (5U)
#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
#define USB_OTG_HCINT_NYET_Pos (6U)
#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
#define USB_OTG_HCINT_TXERR_Pos (7U)
#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
#define USB_OTG_HCINT_BBERR_Pos (8U)
#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
#define USB_OTG_HCINT_FRMOR_Pos (9U)
#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
#define USB_OTG_HCINT_DTERR_Pos (10U)
#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
#define USB_OTG_DIEPINT_XFRC_Pos (0U)
#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DIEPINT_TOC_Pos (3U)
#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
#define USB_OTG_DIEPINT_TXFE_Pos (7U)
#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BNA_Pos (9U)
#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos (12U)
#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos (13U)
#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
#define USB_OTG_HCINTMSK_NYET_Pos (6U)
#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
#define USB_OTG_HCTSIZ_DPID_Pos (29U)
#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition forUSB_OTG_HCDMA register ********************/
#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
#define USB_OTG_DOEPCTL_STALL_Pos (21U)
#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
#define USB_OTG_DOEPINT_XFRC_Pos (0U)
#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_STUP_Pos (3U)
#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_NYET_Pos (14U)
#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
/******************** Bit definition for PCGCCTL register ********************/
#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON ||\
(INSTANCE) == ADC3_COMMON)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
/******************** COMP Instances with window mode capability **************/
#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/******************************* DCMI Instances *******************************/
#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
/****************************** DFSDM Instances *******************************/
#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
((INSTANCE) == DFSDM1_Filter1) || \
((INSTANCE) == DFSDM1_Filter2) || \
((INSTANCE) == DFSDM1_Filter3))
#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
((INSTANCE) == DFSDM1_Channel1) || \
((INSTANCE) == DFSDM1_Channel2) || \
((INSTANCE) == DFSDM1_Channel3) || \
((INSTANCE) == DFSDM1_Channel4) || \
((INSTANCE) == DFSDM1_Channel5) || \
((INSTANCE) == DFSDM1_Channel6) || \
((INSTANCE) == DFSDM1_Channel7))
/******************************** DMA Instances *******************************/
#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
((INSTANCE) == DMA1_Stream1) || \
((INSTANCE) == DMA1_Stream2) || \
((INSTANCE) == DMA1_Stream3) || \
((INSTANCE) == DMA1_Stream4) || \
((INSTANCE) == DMA1_Stream5) || \
((INSTANCE) == DMA1_Stream6) || \
((INSTANCE) == DMA1_Stream7) || \
((INSTANCE) == DMA2_Stream0) || \
((INSTANCE) == DMA2_Stream1) || \
((INSTANCE) == DMA2_Stream2) || \
((INSTANCE) == DMA2_Stream3) || \
((INSTANCE) == DMA2_Stream4) || \
((INSTANCE) == DMA2_Stream5) || \
((INSTANCE) == DMA2_Stream6) || \
((INSTANCE) == DMA2_Stream7) || \
((INSTANCE) == BDMA_Channel0) || \
((INSTANCE) == BDMA_Channel1) || \
((INSTANCE) == BDMA_Channel2) || \
((INSTANCE) == BDMA_Channel3) || \
((INSTANCE) == BDMA_Channel4) || \
((INSTANCE) == BDMA_Channel5) || \
((INSTANCE) == BDMA_Channel6) || \
((INSTANCE) == BDMA_Channel7))
/******************************** DMA Request Generator Instances **************/
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3) || \
((INSTANCE) == DMAMUX1_RequestGenerator4) || \
((INSTANCE) == DMAMUX1_RequestGenerator5) || \
((INSTANCE) == DMAMUX1_RequestGenerator6) || \
((INSTANCE) == DMAMUX1_RequestGenerator7) || \
((INSTANCE) == DMAMUX2_RequestGenerator0) || \
((INSTANCE) == DMAMUX2_RequestGenerator1) || \
((INSTANCE) == DMAMUX2_RequestGenerator2) || \
((INSTANCE) == DMAMUX2_RequestGenerator3) || \
((INSTANCE) == DMAMUX2_RequestGenerator4) || \
((INSTANCE) == DMAMUX2_RequestGenerator5) || \
((INSTANCE) == DMAMUX2_RequestGenerator6) || \
((INSTANCE) == DMAMUX2_RequestGenerator7))
/******************************* DMA2D Instances *******************************/
#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
/******************************** MDMA Request Generator Instances **************/
#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
((INSTANCE) == MDMA_Channel1) || \
((INSTANCE) == MDMA_Channel2) || \
((INSTANCE) == MDMA_Channel3) || \
((INSTANCE) == MDMA_Channel4) || \
((INSTANCE) == MDMA_Channel5) || \
((INSTANCE) == MDMA_Channel6) || \
((INSTANCE) == MDMA_Channel7) || \
((INSTANCE) == MDMA_Channel8) || \
((INSTANCE) == MDMA_Channel9) || \
((INSTANCE) == MDMA_Channel10) || \
((INSTANCE) == MDMA_Channel11) || \
((INSTANCE) == MDMA_Channel12) || \
((INSTANCE) == MDMA_Channel13) || \
((INSTANCE) == MDMA_Channel14) || \
((INSTANCE) == MDMA_Channel15))
/******************************* QUADSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/******************************* FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
((__INSTANCE__) == FDCAN2))
#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG) || \
((INSTANCE) == GPIOH) || \
((INSTANCE) == GPIOI) || \
((INSTANCE) == GPIOJ) || \
((INSTANCE) == GPIOK))
/**************************** GPIO Lock Instances *****************************/
/* On H7, all GPIO Bank support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** HSEM Instances *******************************/
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
#define HSEM_CM7_MASTERID (0x00000003U) /* Semaphore Master CM7 ID */
#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/************** I2C Instances : wakeup capability from stop modes *************/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/******************************** SMBUS Instances *****************************/
#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5) || \
((INSTANCE) == SPI6))
#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/******************************** SWPMI Instances *****************************/
#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
((INSTANCE) == LPTIM2) || \
((INSTANCE) == LPTIM3) ||\
((INSTANCE) == LPTIM4) ||\
((INSTANCE) == LPTIM5))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 5 capture/compare channels *************/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 6 capture/compare channels *************/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************** TIM Instances : Advanced-control timers *****************/
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : DMA requests generation (UDE) *************/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (CCxDE) *****************/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (COMDE) *****************/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/***************** TIM Instances : external trigger reamp input availabe *******/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/***************** TIM Instances : external trigger reamp input availabe *******/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12))
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting commutation event *************/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1)|| \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM13) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM14) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 2 **********/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
/****************** TIM Instances : TIM_32B_COUNTER ***************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/****************** TIM Instances : TIM_BKIN2 ***************************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************************** HRTIM Instances *******************************/
#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/****************** UART Instances : Auto Baud Rate detection *****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/*********************** UART Instances : Driver Enable ***********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8) || \
((INSTANCE) == LPUART1))
/********************* UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8) || \
((INSTANCE) == LPUART1))
/******************* UART Instances : Hardware Flow control *******************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8) || \
((INSTANCE) == LPUART1))
/************************* UART Instances : LIN mode **************************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/****************** UART Instances : Wake-up from Stop mode *******************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8) || \
((INSTANCE) == LPUART1))
/************************* UART Instances : IRDA mode *************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/********************* USART Instances : Smard card mode **********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/****************************** LPUART Instance *******************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
/****************************** MDIOS Instances ********************************/
#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
/****************************** SAI Instances ********************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
((INSTANCE) == SAI1_Block_B) || \
((INSTANCE) == SAI2_Block_A) || \
((INSTANCE) == SAI2_Block_B) || \
((INSTANCE) == SAI3_Block_A) || \
((INSTANCE) == SAI3_Block_B) || \
((INSTANCE) == SAI4_Block_A) || \
((INSTANCE) == SAI4_Block_B))
/****************************** SPDIFRX Instances ********************************/
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2))
#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
/******************************************************************************/
/* For a painless codes migration between the STM32H7xx device product */
/* lines, or with STM32F7xx devices the aliases defined below are put */
/* in place to overcome the differences in the interrupt handlers and IRQn */
/* definitions. No need to update developed interrupt code when moving */
/* across product lines within the same STM32H7 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define RNG_IRQn HASH_RNG_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define PVD_IRQn PVD_AVD_IRQn
/* Aliases for __IRQHandler */
#define RNG_IRQHandler HASH_RNG_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define PVD_IRQHandler PVD_AVD_IRQHandler
/**
* @}
*/
/****************************** Product define *********************************/
#define FLASH_SIZE 0x200000 /* 2MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1MB */
#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32H7xx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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