352 lines
9.7 KiB
C
352 lines
9.7 KiB
C
/*
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Copyright (C) 2014..2017 Marco Veeneman
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file hal_adc_lld.c
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* @brief PLATFORM ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC0 driver identifier.*/
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#if TIVA_ADC_USE_ADC0 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/** @brief ADC1 driver identifier.*/
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#if TIVA_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Common IRQ handler.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void serve_interrupt(ADCDriver *adcp)
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{
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tiva_udma_table_entry_t *pri = &udmaControlTable.primary[adcp->dmanr];
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tiva_udma_table_entry_t *alt = &udmaControlTable.alternate[adcp->dmanr];
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if ((pri->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) {
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/* Primary is used only for circular transfers */
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if (adcp->grpp->circular) {
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if (adcp->depth > 1) {
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_adc_isr_half_code(adcp);
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}
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/* Reconfigure DMA for new lower half transfer */
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pri->chctl = adcp->prictl;
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}
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}
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if ((alt->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) {
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/* Alternate is used for both linear and circular transfers */
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_adc_isr_full_code(adcp);
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if (adcp->grpp->circular) {
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/* Reconfigure DMA for new upper half transfer */
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alt->chctl = adcp->altctl;
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if TIVA_ADC_USE_ADC0
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/**
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* @brief ADC0 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(TIVA_ADC0_SEQ0_HANDLER)
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{
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&ADCD1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if TIVA_ADC_USE_ADC1
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/**
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* @brief ADC1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(TIVA_ADC1_SEQ0_HANDLER)
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{
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&ADCD2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void)
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{
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#if TIVA_ADC_USE_ADC0
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC0_BASE;
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ADCD1.dmanr = TIVA_ADC_ADC0_SS0_UDMA_CHANNEL;
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ADCD1.chnmap = TIVA_ADC_ADC0_SS0_UDMA_MAPPING;
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#endif
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#if TIVA_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD2);
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ADCD2.adc = ADC1_BASE;
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ADCD2.dmanr = TIVA_ADC_ADC1_SS0_UDMA_CHANNEL;
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ADCD2.chnmap = TIVA_ADC_ADC1_SS0_UDMA_MAPPING;
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#endif
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp)
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{
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if (adcp->state == ADC_STOP) {
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/* Enables the peripheral.*/
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#if TIVA_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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bool b;
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b = udmaChannelAllocate(adcp->dmanr);
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osalDbgAssert(!b, "channel already allocated");
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HWREG(SYSCTL_RCGCADC) |= (1 << 0);
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while (!(HWREG(SYSCTL_PRADC) & (1 << 0)))
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;
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/* Only sequencer 0 is supported */
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nvicEnableVector(TIVA_ADC0_SEQ0_NUMBER, TIVA_ADC0_SEQ0_PRIORITY);
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}
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#endif
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#if TIVA_ADC_USE_ADC1
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if (&ADCD2 == adcp) {
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bool b;
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b = udmaChannelAllocate(adcp->dmanr);
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osalDbgAssert(!b, "channel already allocated");
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HWREG(SYSCTL_RCGCADC) |= (1 << 1);
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while (!(HWREG(SYSCTL_PRADC) & (1 << 1)))
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;
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/* Only sequencer 0 is supported */
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nvicEnableVector(TIVA_ADC1_SEQ0_NUMBER, TIVA_ADC1_SEQ0_PRIORITY);
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}
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#endif
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HWREG(UDMA_CHMAP0 + (adcp->dmanr / 8) * 4) |= (adcp->chnmap << (adcp->dmanr % 8));
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp)
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{
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if (adcp->state == ADC_READY) {
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/* Resets the peripheral.*/
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udmaChannelRelease(adcp->dmanr);
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/* Disables the peripheral.*/
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#if TIVA_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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nvicDisableVector(TIVA_ADC0_SEQ0_NUMBER);
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}
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#endif
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#if TIVA_ADC_USE_ADC1
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if (&ADCD2 == adcp) {
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nvicDisableVector(TIVA_ADC1_SEQ0_NUMBER);
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}
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp)
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{
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uint32_t adc = adcp->adc;
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tiva_udma_table_entry_t *primary = &udmaControlTable.primary[adcp->dmanr];
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tiva_udma_table_entry_t *alternate = &udmaControlTable.alternate[adcp->dmanr];
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/* Disable sample sequencer 0 */
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HWREG(adc + ADC_O_ACTSS) &= (1 << 0);
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/* Configure the sample sequencer 0 trigger */
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HWREG(adc + ADC_O_EMUX) = adcp->grpp->emux & 0xff;
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/* If pwm is used as trigger, select in which block the pwm generator is
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located */
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if (adcp->grpp->emux >= 6 && adcp->grpp->emux <= 9) {
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HWREG(adc + ADC_O_TSSEL) = 0;
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}
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/* For each sample in the sample sequencer, select the input source */
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HWREG(adc + ADC_O_SSMUX0) = adcp->grpp->ssmux;
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/* Configure the sample control bits */
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HWREG(adc + ADC_O_SSCTL0) = adcp->grpp->ssctl | 0x44444444; /* Enforce IEn bits */
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/* Alternate source endpoint is the same for all transfers */
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alternate->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0);
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/* Configure DMA */
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if ((adcp->grpp->circular) && (adcp->depth > 1)) {
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/* Configure DMA in ping-pong mode.
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Ping (1st half) is configured in the primary control structure.
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Pong (2nd half) is configured in the alternate control structure. */
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uint32_t ctl;
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/* configure the primary source endpoint */
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primary->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0);
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/* sample buffer is split in half, the upper half is used here */
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primary->dstendp = (void *)(adcp->samples +
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(adcp->grpp->num_channels * adcp->depth / 2) - 1);
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/* the lower half is used here */
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alternate->dstendp = (void *)(adcp->samples +
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(adcp->grpp->num_channels * adcp->depth) - 1);
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ctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 |
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UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE |
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UDMA_CHCTL_ARBSIZE_1 |
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UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth / 2) |
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UDMA_CHCTL_XFERMODE_PINGPONG;
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adcp->prictl = ctl;
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adcp->altctl = ctl;
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dmaChannelPrimary(adcp->dmanr);
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}
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else {
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/* Configure the DMA in basic mode.
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This is used for both circular buffers with a depth of 1 and linear
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buffers.*/
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alternate->dstendp = (void *)(adcp->samples +
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(adcp->grpp->num_channels * adcp->depth) - 1);
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adcp->prictl = UDMA_CHCTL_XFERMODE_STOP;
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adcp->altctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 |
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UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE |
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UDMA_CHCTL_ARBSIZE_1 |
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UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth) |
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UDMA_CHCTL_XFERMODE_BASIC;
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dmaChannelAlternate(adcp->dmanr);
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}
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/* Configure primary and alternate channel control fields */
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primary->chctl = adcp->prictl;
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alternate->chctl = adcp->altctl;
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/* Configure DMA channel */
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dmaChannelBurstOnly(adcp->dmanr);
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dmaChannelPriorityDefault(adcp->dmanr);
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dmaChannelEnableRequest(adcp->dmanr);
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/* Enable DMA channel */
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dmaChannelEnable(adcp->dmanr);
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/* Enable the sample sequencer */
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HWREG(adc + ADC_O_ACTSS) |= (1 << 0);
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/* Enable DMA on the sample sequencer, is this for 129x only?*/
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//HWREG(adc + ADC_O_ACTSS) |= (1 << 8);
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/* Start conversion if configured for CPU trigger */
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if ((adcp->grpp->emux & 0xff) == 0) {
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HWREG(adc + ADC_O_PSSI) = ADC_PSSI_SS0;
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}
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp)
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{
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uint32_t adc = adcp->adc;
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/* Stop ongoing DMA transfer */
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dmaChannelDisable(adcp->dmanr);
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/* Stop ongoing ADC conversion by disabling the active sample sequencer */
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HWREG(adc + ADC_O_ACTSS) &= ~(1 << 0);
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}
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#endif /* HAL_USE_ADC == TRUE */
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/** @} */
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