613 lines
17 KiB
C
613 lines
17 KiB
C
/*
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Copyright (C) 2013-2015 Andrea Zoppi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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#include "chprintf.h"
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#include "shell.h"
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#if (HAL_USE_SERIAL_USB == TRUE)
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#include "usbcfg.h"
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#endif
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#include "ili9341.h"
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#include "hal_stm32_ltdc.h"
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#include "hal_stm32_dma2d.h"
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#include "res/wolf3d_vgagraph_chunk87.h"
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/*===========================================================================*/
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/* SDRAM related. */
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/*===========================================================================*/
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// TODO: Move constants below elsewhere, and normalize their name
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/* SDRAM bank base address.*/
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#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
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/*
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* FMC SDRAM Mode definition register defines
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*/
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#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/*
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* FMC_ReadPipe_Delay
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*/
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#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
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#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
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#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
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#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
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/*
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* FMC_Read_Burst
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*/
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#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
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#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
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#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
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/*
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* FMC_SDClock_Period
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*/
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#define FMC_SDClock_Disable ((uint32_t)0x00000000)
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#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
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#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
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#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
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/*
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* FMC_ColumnBits_Number
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*/
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#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
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#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
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#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
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#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
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/*
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* FMC_RowBits_Number
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*/
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#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
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#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
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#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
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/*
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* FMC_SDMemory_Data_Width
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*/
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#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
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#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
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#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
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/*
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* FMC_InternalBank_Number
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*/
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#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
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#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
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/*
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* FMC_CAS_Latency
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*/
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#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
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#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
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#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
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/*
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* FMC_Write_Protection
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*/
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#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
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#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
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/*
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* SDRAM driver configuration structure.
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*/
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static const SDRAMConfig sdram_cfg = {
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.sdcr = (uint32_t)(FMC_ColumnBits_Number_8b |
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FMC_RowBits_Number_12b |
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FMC_SDMemory_Width_16b |
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FMC_InternalBank_Number_4 |
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FMC_CAS_Latency_3 |
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FMC_Write_Protection_Disable |
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FMC_SDClock_Period_2 |
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FMC_Read_Burst_Disable |
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FMC_ReadPipe_Delay_1),
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.sdtr = (uint32_t)((2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
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(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
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(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
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(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
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(2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
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(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
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(2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
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.sdcmr = (uint32_t)(((4 - 1) << 5) |
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((FMC_SDCMR_MRD_BURST_LENGTH_2 |
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
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FMC_SDCMR_MRD_CAS_LATENCY_3 |
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
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/* if (STM32_SYSCLK == 180000000) ->
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64ms / 4096 = 15.625us
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15.625us * 90MHz = 1406 - 20 = 1386 */
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//.sdrtr = (1386 << 1),
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.sdrtr = (uint32_t)(683 << 1),
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};
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/* SDRAM size, in bytes.*/
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#define IS42S16400J_SIZE (8 * 1024 * 1024)
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/*
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* Erases the whole SDRAM bank.
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*/
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static void sdram_bulk_erase(void) {
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volatile uint8_t *p = (volatile uint8_t *)SDRAM_BANK_ADDR;
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volatile uint8_t *end = p + IS42S16400J_SIZE;
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while (p < end)
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*p++ = 0;
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}
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/*
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* Red LED blinker thread, times are in milliseconds.
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*/
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static THD_WORKING_AREA(waThread1, 128);
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static THD_FUNCTION(Thread1, arg) {
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(void)arg;
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chRegSetThreadName("blinker1");
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while (true) {
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palClearPad(GPIOG, GPIOG_LED4_RED);
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chThdSleepMilliseconds(500);
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palSetPad(GPIOG, GPIOG_LED4_RED);
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chThdSleepMilliseconds(500);
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}
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}
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/*
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* Green LED blinker thread, times are in milliseconds.
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*/
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static THD_WORKING_AREA(waThread2, 128);
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static THD_FUNCTION(Thread2, arg) {
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(void)arg;
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chRegSetThreadName("blinker2");
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while (true) {
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palClearPad(GPIOG, GPIOG_LED3_GREEN);
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chThdSleepMilliseconds(250);
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palSetPad(GPIOG, GPIOG_LED3_GREEN);
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chThdSleepMilliseconds(250);
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}
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}
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/*===========================================================================*/
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/* LTDC related. */
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/*===========================================================================*/
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static uint8_t frame_buffer[240 * 320 * 3] __attribute__((section(".ram7")));
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static uint8_t view_buffer[240 * 320];
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extern const ltdc_color_t wolf3d_palette[256];
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static const ltdc_window_t ltdc_fullscreen_wincfg = {
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0,
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240 - 1,
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0,
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320 - 1,
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};
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static const ltdc_frame_t ltdc_view_frmcfg1 = {
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view_buffer,
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240,
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320,
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240 * sizeof(uint8_t),
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LTDC_FMT_L8,
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};
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static const ltdc_laycfg_t ltdc_view_laycfg1 = {
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<dc_view_frmcfg1,
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<dc_fullscreen_wincfg,
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LTDC_COLOR_FUCHSIA,
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0xFF,
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0x980088,
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wolf3d_palette,
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256,
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LTDC_BLEND_FIX1_FIX2,
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(LTDC_LEF_ENABLE | LTDC_LEF_PALETTE),
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};
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static const ltdc_frame_t ltdc_screen_frmcfg1 = {
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frame_buffer,
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240,
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320,
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240 * 3,
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LTDC_FMT_RGB888,
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};
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static const ltdc_laycfg_t ltdc_screen_laycfg1 = {
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<dc_screen_frmcfg1,
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<dc_fullscreen_wincfg,
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LTDC_COLOR_FUCHSIA,
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0xFF,
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0x980088,
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NULL,
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0,
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LTDC_BLEND_FIX1_FIX2,
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LTDC_LEF_ENABLE,
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};
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static const LTDCConfig ltdc_cfg = {
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/* Display specifications.*/
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240, /**< Screen pixel width.*/
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320, /**< Screen pixel height.*/
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10, /**< Horizontal sync pixel width.*/
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2, /**< Vertical sync pixel height.*/
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20, /**< Horizontal back porch pixel width.*/
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2, /**< Vertical back porch pixel height.*/
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10, /**< Horizontal front porch pixel width.*/
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4, /**< Vertical front porch pixel height.*/
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0, /**< Driver configuration flags.*/
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/* ISR callbacks.*/
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NULL, /**< Line Interrupt ISR, or @p NULL.*/
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NULL, /**< Register Reload ISR, or @p NULL.*/
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NULL, /**< FIFO Underrun ISR, or @p NULL.*/
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NULL, /**< Transfer Error ISR, or @p NULL.*/
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/* Color and layer settings.*/
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LTDC_COLOR_TEAL,
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<dc_view_laycfg1,
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NULL,
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};
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extern LTDCDriver LTDCD1;
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const SPIConfig spi_cfg5 = {
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false,
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NULL,
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GPIOC,
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GPIOC_SPI5_LCD_CS,
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(((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
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0
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};
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extern SPIDriver SPID5;
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const ILI9341Config ili9341_cfg = {
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&SPID5,
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GPIOD,
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GPIOD_LCD_WRX
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};
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static void initialize_lcd(void) {
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static const uint8_t pgamma[15] = {
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0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
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0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00
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};
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static const uint8_t ngamma[15] = {
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0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
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0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F
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};
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ILI9341Driver *const lcdp = &ILI9341D1;
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/* XOR-checkerboard texture.*/
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unsigned x, y;
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for (y = 0; y < 320; ++y)
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for (x = 0; x < 240; ++x)
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view_buffer[y * 240 + x] = (uint8_t)(x ^ y);
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ili9341AcquireBus(lcdp);
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ili9341Select(lcdp);
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ili9341WriteCommand(lcdp, ILI9341_SET_FRAME_CTL_NORMAL);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x1B);
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ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
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ili9341WriteByte(lcdp, 0x0A);
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ili9341WriteByte(lcdp, 0xA2);
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ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_1);
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ili9341WriteByte(lcdp, 0x10);
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ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_2);
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ili9341WriteByte(lcdp, 0x10);
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ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_1);
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ili9341WriteByte(lcdp, 0x45);
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ili9341WriteByte(lcdp, 0x15);
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ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_2);
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ili9341WriteByte(lcdp, 0x90);
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ili9341WriteCommand(lcdp, ILI9341_SET_MEM_ACS_CTL);
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ili9341WriteByte(lcdp, 0xC8);
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ili9341WriteCommand(lcdp, ILI9341_SET_RGB_IF_SIG_CTL);
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ili9341WriteByte(lcdp, 0xC2);
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ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
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ili9341WriteByte(lcdp, 0x0A);
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ili9341WriteByte(lcdp, 0xA7);
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ili9341WriteByte(lcdp, 0x27);
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ili9341WriteByte(lcdp, 0x04);
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ili9341WriteCommand(lcdp, ILI9341_SET_COL_ADDR);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0xEF);
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ili9341WriteCommand(lcdp, ILI9341_SET_PAGE_ADDR);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x01);
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ili9341WriteByte(lcdp, 0x3F);
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ili9341WriteCommand(lcdp, ILI9341_SET_IF_CTL);
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ili9341WriteByte(lcdp, 0x01);
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ili9341WriteByte(lcdp, 0x00);
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ili9341WriteByte(lcdp, 0x06);
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ili9341WriteCommand(lcdp, ILI9341_SET_GAMMA);
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ili9341WriteByte(lcdp, 0x01);
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ili9341WriteCommand(lcdp, ILI9341_SET_PGAMMA);
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ili9341WriteChunk(lcdp, pgamma, 15);
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ili9341WriteCommand(lcdp, ILI9341_SET_NGAMMA);
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ili9341WriteChunk(lcdp, ngamma, 15);
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ili9341WriteCommand(lcdp, ILI9341_CMD_SLEEP_OFF);
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chThdSleepMilliseconds(10);
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ili9341WriteCommand(lcdp, ILI9341_CMD_DISPLAY_ON);
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ili9341WriteCommand(lcdp, ILI9341_SET_MEM);
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chThdSleepMilliseconds(10);
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ili9341Unselect(lcdp);
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ili9341ReleaseBus(lcdp);
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}
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static const DMA2DConfig dma2d_cfg = {
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/* ISR callbacks.*/
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NULL, /**< Configuration error, or @p NULL.*/
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NULL, /**< Palette transfer done, or @p NULL.*/
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NULL, /**< Palette access error, or @p NULL.*/
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NULL, /**< Transfer watermark, or @p NULL.*/
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NULL, /**< Transfer complete, or @p NULL.*/
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NULL /**< Transfer error, or @p NULL.*/
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};
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static const dma2d_palcfg_t dma2d_palcfg = {
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wolf3d_palette,
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256,
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DMA2D_FMT_ARGB8888
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};
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static const dma2d_laycfg_t dma2d_bg_laycfg = {
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view_buffer,
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0,
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DMA2D_FMT_L8,
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DMA2D_COLOR_RED,
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0xFF,
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&dma2d_palcfg
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};
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static const dma2d_laycfg_t dma2d_fg_laycfg = {
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(void *)wolf3d_vgagraph_chunk87,
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0,
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DMA2D_FMT_L8,
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DMA2D_COLOR_LIME,
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0xFF,
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&dma2d_palcfg
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};
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static const dma2d_laycfg_t dma2d_frame_laycfg = {
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frame_buffer,
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0,
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DMA2D_FMT_RGB888,
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DMA2D_COLOR_BLUE,
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0xFF,
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NULL
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};
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static void dma2d_test(void) {
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DMA2DDriver *const dma2dp = &DMA2DD1;
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LTDCDriver *const ltdcp = <DCD1;
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chThdSleepSeconds(1);
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ltdcBgSetConfig(ltdcp, <dc_screen_laycfg1);
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ltdcReload(ltdcp, TRUE);
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dma2dAcquireBus(dma2dp);
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/* Target the frame buffer by default.*/
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dma2dBgSetConfig(dma2dp, &dma2d_frame_laycfg);
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dma2dFgSetConfig(dma2dp, &dma2d_frame_laycfg);
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dma2dOutSetConfig(dma2dp, &dma2d_frame_laycfg);
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/* Copy the background.*/
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dma2dFgSetConfig(dma2dp, &dma2d_bg_laycfg);
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dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
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dma2dJobSetSize(dma2dp, 240, 320);
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dma2dJobExecute(dma2dp);
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/* Draw the splashscren picture at (8, 0).*/
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dma2dFgSetConfig(dma2dp, &dma2d_fg_laycfg);
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dma2dOutSetAddress(dma2dp, dma2dComputeAddress(
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frame_buffer, ltdc_screen_frmcfg1.pitch, DMA2D_FMT_RGB888, 8, 0
|
|
));
|
|
dma2dOutSetWrapOffset(dma2dp, ltdc_screen_frmcfg1.width - 200);
|
|
dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
|
|
dma2dJobSetSize(dma2dp, 200, 320);
|
|
dma2dJobExecute(dma2dp);
|
|
|
|
dma2dReleaseBus(dma2dp);
|
|
}
|
|
|
|
/*===========================================================================*/
|
|
/* Command line related. */
|
|
/*===========================================================================*/
|
|
|
|
|
|
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
|
|
#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
|
|
|
|
static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
|
|
(void)argv;
|
|
if (argc > 0) {
|
|
chprintf(chp, "Usage: reset\r\n");
|
|
return;
|
|
}
|
|
|
|
chprintf(chp, "Will reset in 200ms\r\n");
|
|
chThdSleepMilliseconds(200);
|
|
NVIC_SystemReset();
|
|
}
|
|
|
|
static const ShellCommand commands[] = {
|
|
{"reset", cmd_reset},
|
|
{NULL, NULL}
|
|
};
|
|
|
|
static const ShellConfig shell_cfg1 = {
|
|
#if (HAL_USE_SERIAL_USB == TRUE)
|
|
(BaseSequentialStream *)&SDU2,
|
|
#else
|
|
(BaseSequentialStream *)&SD1,
|
|
#endif
|
|
commands
|
|
};
|
|
|
|
/*===========================================================================*/
|
|
/* Initialization and main thread. */
|
|
/*===========================================================================*/
|
|
|
|
/*
|
|
* Application entry point.
|
|
*/
|
|
int main(void) {
|
|
thread_t *shelltp = NULL;
|
|
|
|
/*
|
|
* System initializations.
|
|
* - HAL initialization, this also initializes the configured device drivers
|
|
* and performs the board-specific initializations.
|
|
* - Kernel initialization, the main() function becomes a thread and the
|
|
* RTOS is active.
|
|
*/
|
|
halInit();
|
|
chSysInit();
|
|
|
|
/*
|
|
* Shell manager initialization.
|
|
*/
|
|
shellInit();
|
|
|
|
#if (HAL_USE_SERIAL_USB == TRUE)
|
|
/*
|
|
* Initializes a serial-over-USB CDC driver.
|
|
*/
|
|
sduObjectInit(&SDU2);
|
|
sduStart(&SDU2, &serusbcfg);
|
|
|
|
/*
|
|
* Activates the USB driver and then the USB bus pull-up on D+.
|
|
* Note, a delay is inserted in order to not have to disconnect the cable
|
|
* after a reset.
|
|
*/
|
|
usbDisconnectBus(serusbcfg.usbp);
|
|
chThdSleepMilliseconds(1000);
|
|
usbStart(serusbcfg.usbp, &usbcfg);
|
|
usbConnectBus(serusbcfg.usbp);
|
|
#else
|
|
/*
|
|
* Initializes serial port.
|
|
*/
|
|
sdStart(&SD1, NULL);
|
|
#endif /* HAL_USE_SERIAL_USB */
|
|
|
|
/*
|
|
* Initialise FSMC for SDRAM.
|
|
*/
|
|
sdramInit();
|
|
sdramStart(&SDRAMD1, &sdram_cfg);
|
|
sdram_bulk_erase();
|
|
|
|
/*
|
|
* Activates the LCD-related drivers.
|
|
*/
|
|
spiStart(&SPID5, &spi_cfg5);
|
|
ili9341ObjectInit(&ILI9341D1);
|
|
ili9341Start(&ILI9341D1, &ili9341_cfg);
|
|
initialize_lcd();
|
|
ltdcInit();
|
|
ltdcStart(<DCD1, <dc_cfg);
|
|
|
|
/*
|
|
* Activates the DMA2D-related drivers.
|
|
*/
|
|
dma2dInit();
|
|
dma2dStart(&DMA2DD1, &dma2d_cfg);
|
|
dma2d_test();
|
|
|
|
/*
|
|
* Creating the blinker threads.
|
|
*/
|
|
chThdCreateStatic(waThread1, sizeof(waThread1),
|
|
NORMALPRIO + 10, Thread1, NULL);
|
|
chThdCreateStatic(waThread2, sizeof(waThread2),
|
|
NORMALPRIO + 10, Thread2, NULL);
|
|
|
|
/*
|
|
* Normal main() thread activity, in this demo it just performs
|
|
* a shell respawn upon its termination.
|
|
*/
|
|
while (true) {
|
|
if (!shelltp) {
|
|
#if (HAL_USE_SERIAL_USB == TRUE)
|
|
if (SDU2.config->usbp->state == USB_ACTIVE) {
|
|
/* Spawns a new shell.*/
|
|
shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO, shellThread, (void *) &shell_cfg1);
|
|
}
|
|
#else
|
|
shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO, shellThread, (void *) &shell_cfg1);
|
|
#endif
|
|
}
|
|
else {
|
|
/* If the previous shell exited.*/
|
|
if (chThdTerminatedX(shelltp)) {
|
|
/* Recovers memory of the previous shell.*/
|
|
chThdRelease(shelltp);
|
|
shelltp = NULL;
|
|
}
|
|
}
|
|
chThdSleepMilliseconds(500);
|
|
}
|
|
}
|