176 lines
5.5 KiB
ArmAsm
176 lines
5.5 KiB
ArmAsm
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCMAx-TZ/compilers/GCC/chcoreasm.S
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* @brief ARMCMAx-TZ architecture port low level code.
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*
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* @addtogroup ARMCMAx-TZ_CORE
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* @{
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*/
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#define _FROM_ASM_
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#include "chlicense.h"
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#include "chconf.h"
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#include "armparams.h"
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#define FALSE 0
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#define TRUE 1
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#if !defined(__DOXYGEN__)
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/*
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* RTOS-specific context offset.
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*/
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#if defined(_CHIBIOS_RT_CONF_)
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#define CONTEXT_OFFSET 12
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#elif defined(_CHIBIOS_NIL_CONF_)
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#define CONTEXT_OFFSET 0
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#else
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#error "invalid chconf.h"
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#endif
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_MON, 0x16
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.set I_BIT, 0x80
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.set F_BIT, 0x40
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.text
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.balign 16
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.code 32
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.global _port_switch_arm
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_port_switch_arm:
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stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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str sp, [r1, #12]
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ldr sp, [r0, #12]
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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/*
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* Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address
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* of a register holding the address of the ISR to be invoked, the ISR
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* then returns in the common epilogue code where the context switch will
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* be performed, if required.
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | r12 | |
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* | r3 | |
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* | r2 | | External context: IRQ handler frame
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* | r1 | |
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* | r0 | |
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* | LR_FIQ | | (user code return address)
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* | PSR_USR | -+ (user code status)
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* | .... | <- chSchDoReschedule() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | r11 | |
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* | r10 | |
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* | r9 | |
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* | r8 | | Internal context: chSysSwitch() frame
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* | r7 | |
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* | r6 | |
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* | r5 | |
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* SP-> | r4 | -+
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* Low +------------+
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*
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*/
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.balign 16
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.code 32
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.global Fiq_Handler
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Fiq_Handler:
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// the fiq is taken locally from secure state
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// current mode is fiq
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stmfd sp!, {r0-r3, r12, lr} // save scratch registers and lr
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ldr r0, =ARM_IRQ_VECTOR_REG
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ldr r0, [r0]
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ldr lr, =_fiq_ret_arm // ISR return point.
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bx r0 // Calling the ISR.
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_fiq_ret_arm:
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cmp r0, #0
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ldmfd sp!, {r0-r3, r12, lr}
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subeqs pc, lr, #4 // No reschedule, returns.
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// Now the frame is created in the system stack of the current
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// thread, the IRQ stack is empty.
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msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
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stmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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mrs r0, SPSR
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mov r1, lr
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msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
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stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_FIQ.
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// Context switch.
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_lock
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#endif
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bl chSchDoReschedule
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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// Re-establish the IRQ conditions again.
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ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_FIQ.
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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msr SPSR_fsxc, r0
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mov lr, r1
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msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
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ldmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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subs pc, lr, #4
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/*
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* Threads trampoline code.
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* NOTE: The threads always start in ARM mode.
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*/
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.balign 16
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.code 32
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.globl _port_thread_start
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_port_thread_start:
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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msr CPSR_c, #MODE_SYS
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mov r0, r5
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mov lr, pc
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bx r4
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#if defined(_CHIBIOS_RT_CONF_)
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mov r0, #0 /* MSG_OK */
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bl chThdExit
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_zombies: b _zombies
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#endif
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#if defined(_CHIBIOS_NIL_CONF_)
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mov r0, #0
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bl chSysHalt
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#endif
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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