177 lines
8.2 KiB
C
177 lines
8.2 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file hal_mii.h
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* @brief MII macros and structures.
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*
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* @addtogroup MII
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* @{
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*/
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#ifndef MII_H
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#define MII_H
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/**
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* @name Generic MII registers
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* @{
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*/
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#define MII_BMCR 0x00 /**< Basic mode control register. */
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#define MII_BMSR 0x01 /**< Basic mode status register. */
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#define MII_PHYSID1 0x02 /**< PHYS ID 1. */
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#define MII_PHYSID2 0x03 /**< PHYS ID 2. */
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#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */
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#define MII_LPA 0x05 /**< Link partner ability reg. */
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#define MII_EXPANSION 0x06 /**< Expansion register. */
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#define MII_ANNPTR 0x07 /**< 1000BASE-T control. */
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#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */
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#define MII_STAT1000 0x0a /**< 1000BASE-T status. */
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#define MII_ESTATUS 0x0f /**< Extended Status. */
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#define MII_PHYSTS 0x10 /**< PHY Status register. */
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#define MII_MICR 0x11 /**< MII Interrupt ctrl register. */
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#define MII_DCOUNTER 0x12 /**< Disconnect counter. */
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#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */
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#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */
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#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */
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#define MII_SREVISION 0x16 /**< Silicon revision. */
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#define MII_RESV1 0x17 /**< Reserved. */
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#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */
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#define MII_PHYADDR 0x19 /**< PHY address. */
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#define MII_RESV2 0x1a /**< Reserved. */
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#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */
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#define MII_NCONFIG 0x1c /**< Network interface config. */
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/** @} */
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/**
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* @name Basic mode control register
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* @{
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*/
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#define BMCR_RESV 0x007f /**< Unused. */
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#define BMCR_CTST 0x0080 /**< Collision test. */
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#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */
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#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */
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#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */
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#define BMCR_PDOWN 0x0800 /**< Powerdown. */
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#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */
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#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */
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#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */
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#define BMCR_RESET 0x8000 /**< Reset. */
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/** @} */
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/**
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* @name Basic mode status register
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* @{
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*/
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#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */
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#define BMSR_JCD 0x0002 /**< Jabber detected. */
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#define BMSR_LSTATUS 0x0004 /**< Link status. */
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#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */
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#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */
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#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */
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#define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */
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#define BMSR_RESV 0x0780 /**< Unused. */
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#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */
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#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */
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#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */
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#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */
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#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */
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/** @} */
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/**
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* @name Advertisement control register
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* @{
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*/
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#define ADVERTISE_SLCT 0x001f /**< Selector bits. */
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#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */
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#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */
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#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */
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#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */
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#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */
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#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */
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#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */
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#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */
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#define ADVERTISE_RESV 0x1000 /**< Unused. */
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#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */
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#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */
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#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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ADVERTISE_CSMA)
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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/** @} */
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/**
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* @name Link partner ability register
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* @{
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*/
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#define LPA_SLCT 0x001f /**< Same as advertise selector. */
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#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */
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#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */
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#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */
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#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */
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#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */
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#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */
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#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */
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#define LPA_RESV 0x1000 /**< Unused. */
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#define LPA_RFAULT 0x2000 /**< Link partner faulted. */
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#define LPA_LPACK 0x4000 /**< Link partner acked us. */
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#define LPA_NPAGE 0x8000 /**< Next page bit. */
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#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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/** @} */
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/**
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* @name Expansion register for auto-negotiation
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* @{
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*/
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#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */
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#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */
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#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */
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#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */
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#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */
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#define EXPANSION_RESV 0xffe0 /**< Unused. */
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/** @} */
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/**
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* @name N-way test register
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* @{
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*/
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#define NWAYTEST_RESV1 0x00ff /**< Unused. */
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#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */
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#define NWAYTEST_RESV2 0xfe00 /**< Unused. */
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/** @} */
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/**
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* @name PHY identifiers
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* @{
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*/
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#define MII_DM9161_ID 0x0181b8a0
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#define MII_AM79C875_ID 0x00225540
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#define MII_KSZ8081_ID 0x00221560
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#define MII_KS8721_ID 0x00221610
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#define MII_STE101P_ID 0x00061C50
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#define MII_DP83848I_ID 0x20005C90
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#define MII_LAN8710A_ID 0x0007C0F1
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#define MII_LAN8720_ID 0x0007C0F0
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#define MII_LAN8742A_ID 0x0007C130
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/** @} */
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#endif /* MII_H */
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/** @} */
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