173 lines
5.6 KiB
C
173 lines
5.6 KiB
C
/*
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ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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SDRAM routines added by Nick Klimov aka progfin.
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*/
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/**
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* @file hal_fsmc_sdram.c
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* @brief SDRAM Driver subsystem low level driver source.
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*
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* @addtogroup SDRAM
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* @{
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*/
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#include "hal.h"
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F745xx) || defined(STM32F746xx) || \
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defined(STM32F756xx) || defined(STM32F767xx) || \
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defined(STM32F769xx) || defined(STM32F777xx) || \
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defined(STM32F779xx))
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#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
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#include "hal_sdram_lld.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* FMC_Command_Mode
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*/
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#define FMCCM_NORMAL ((uint32_t)0x00000000)
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#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001)
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#define FMCCM_PALL ((uint32_t)0x00000002)
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#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003)
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#define FMCCM_LOAD_MODE ((uint32_t)0x00000004)
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#define FMCCM_SELFREFRESH ((uint32_t)0x00000005)
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#define FMCCM_POWER_DOWN ((uint32_t)0x00000006)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief SDRAM driver identifier.
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*/
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SDRAMDriver SDRAMD1;
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/*===========================================================================*/
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/* Driver local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Wait until the SDRAM controller is ready.
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*
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* @notapi
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*/
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static void sdram_lld_wait_ready(void) {
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/* Wait until the SDRAM controller is ready */
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while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY);
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}
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/**
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* @brief Executes the SDRAM memory initialization sequence.
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*
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* @param[in] cfgp pointer to the @p SDRAMConfig object
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*
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* @notapi
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*/
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static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) {
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uint32_t command_target = 0;
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#if STM32_SDRAM_USE_SDRAM1
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command_target |= FMC_SDCMR_CTB1;
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#endif
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#if STM32_SDRAM_USE_SDRAM2
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command_target |= FMC_SDCMR_CTB2;
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#endif
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/* Step 3: Configure a clock configuration enable command.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
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/* Step 4: Insert delay (tipically 100uS).*/
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osalThreadSleepMilliseconds(1);
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/* Step 5: Configure a PALL (precharge all) command.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target;
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/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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/* Step 6.2: Send the second command.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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/* Step 7: Program the external memory mode register.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
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(cfgp->sdcmr & FMC_SDCMR_MRD);
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/* Step 8: Set clock.*/
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sdram_lld_wait_ready();
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SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
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sdram_lld_wait_ready();
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
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{
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sdramp->sdram->SDCR1 = cfgp->sdcr;
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sdramp->sdram->SDTR1 = cfgp->sdtr;
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sdramp->sdram->SDCR2 = cfgp->sdcr;
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sdramp->sdram->SDTR2 = cfgp->sdtr;
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sdram_lld_init_sequence(cfgp);
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}
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void sdram_lld_stop(SDRAMDriver *sdramp) {
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uint32_t command_target = 0;
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#if STM32_SDRAM_USE_SDRAM1
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command_target |= FMC_SDCMR_CTB1;
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#endif
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#if STM32_SDRAM_USE_SDRAM2
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command_target |= FMC_SDCMR_CTB2;
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#endif
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sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
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}
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#endif /* STM32_USE_FSMC_SDRAM */
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#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
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/** @} */
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