114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.io/license.html
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*/
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/**
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* @file drivers/gdisp/RA8875/board_RA8875_marlin.h
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* @brief GDISP Graphic Driver subsystem board interface for the RA8875 display.
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*/
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#ifndef _BOARD_RA8875_H
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#define _BOARD_RA8875_H
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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#define GDISP_RAM (*((volatile gU16 *) 0x68000000)) /* RS = 0 */
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#define GDISP_REG (*((volatile gU16 *) 0x68020000)) /* RS = 1 */
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#define FSMC_BANK 4
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static GFXINLINE void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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// setup for display 0
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case 0: {
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// enable the FSMC peripheral
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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// setup the pin modes for FSMC
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
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IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
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(1 << 13) | (1 << 14) | (1 << 15), 0};
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IOBus busG = {GPIOG, (1 << 10), 0};
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busG, PAL_MODE_ALTERNATE(12));
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// FSMC timing
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FSMC_Bank1->BTCR[FSMC_BANK+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
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| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
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| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
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// Bank1 NOR/SRAM control register configuration
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// This is actually not needed as already set by default after reset
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FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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break;
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}
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// marlin does not have any secondary display so far
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default:
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break;
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}
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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// FSMC delay reduced as the controller now runs at full speed
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FSMC_Bank1->BTCR[2+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
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FSMC_Bank1->BTCR[2] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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}
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static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
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(void) g;
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(void) state;
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}
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static GFXINLINE void acquire_bus(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void release_bus(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void write_index(GDisplay *g, gU16 index) {
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(void) g;
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GDISP_REG = index;
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}
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static GFXINLINE void write_data(GDisplay *g, gU16 data) {
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(void) g;
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GDISP_RAM = data;
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}
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static GFXINLINE void setreadmode(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void setwritemode(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE gU16 read_data(GDisplay *g) {
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(void) g;
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return GDISP_RAM;
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}
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#endif /* _BOARD_RA8875_H */
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