548 lines
16 KiB
C
548 lines
16 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCAx-TZ/chcore.h
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* @brief ARMCAx-TZ architecture port macros and structures.
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*
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* @addtogroup ARMCAx-TZ_CORE
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* @{
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*/
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#ifndef CHCORE_H
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#define CHCORE_H
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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/**
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* @name Port Capabilities and Constants
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* @{
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*/
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/**
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* @brief This port supports a realtime counter.
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*/
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#define PORT_SUPPORTS_RT TRUE
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/**
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* @brief Natural alignment constant.
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* @note It is the minimum alignment for pointer-size variables.
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*/
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#define PORT_NATURAL_ALIGN sizeof (void *)
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/**
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* @brief Stack alignment constant.
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* @note It is the alignment required for the stack pointer.
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*/
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#define PORT_STACK_ALIGN sizeof (stkalign_t)
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/**
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* @brief Working Areas alignment constant.
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* @note It is the alignment to be enforced for thread working areas.
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*/
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#define PORT_WORKING_AREA_ALIGN sizeof (stkalign_t)
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/** @} */
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/**
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* @name Architecture and Compiler
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* @{
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*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define PORT_ARCHITECTURE_ARM_TZ
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/* The following code is not processed when the file is included from an
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asm module because those intrinsic macros are not necessarily defined
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by the assembler too.*/
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#if !defined(_FROM_ASM_)
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/**
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* @brief Compiler name and version.
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*/
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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#define PORT_COMPILER_NAME "GCC " __VERSION__
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#else
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#error "unsupported compiler"
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#endif
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#endif /* !defined(_FROM_ASM_) */
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/** @} */
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/**
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* @name ARM variants
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* @{
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*/
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#define ARM_CORE_CORTEX_A5 105
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#define ARM_CORE_CORTEX_A8 108
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#define ARM_CORE_CORTEX_A9 109
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/** @} */
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/* Inclusion of the ARM implementation specific parameters.*/
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#include "armparams.h"
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Enables an alternative timer implementation.
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* @details Usually the port uses a timer interface defined in the file
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* @p chcore_timer.h, if this option is enabled then the file
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* @p chcore_timer_alt.h is included instead.
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*/
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#if !defined(PORT_USE_ALT_TIMER)
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#define PORT_USE_ALT_TIMER FALSE
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#endif
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p PORT_INT_REQUIRED_STACK.
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* @note In this port it is set to 32 because the idle thread does have
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* a stack frame when compiling without optimizations. You may
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* reduce this value to zero when compiling with optimizations.
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*/
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#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
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#define PORT_IDLE_THREAD_STACK_SIZE 32
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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*/
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#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
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#define PORT_INT_REQUIRED_STACK 32
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#endif
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/**
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* @brief If enabled allows the idle thread to enter a low power mode.
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*/
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#ifndef ARM_ENABLE_WFI_IDLE
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#define ARM_ENABLE_WFI_IDLE FALSE
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/* ARM core check.*/
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#if (ARM_CORE == ARM_CORE_CORTEX_A5) || defined(__DOXYGEN__)
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#define PORT_ARCHITECTURE_ARM_ARM7
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#define PORT_ARCHITECTURE_NAME "ARMv7 (TZ)"
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#define PORT_CORE_VARIANT_NAME "ARM Cortex-A5"
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#elif ARM_CORE == ARM_CORE_CORTEX_A8
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#define PORT_ARCHITECTURE_ARM_CORTEXA8
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#define PORT_ARCHITECTURE_NAME "ARMv7"
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#define PORT_CORE_VARIANT_NAME "ARM Cortex-A8"
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#elif ARM_CORE == ARM_CORE_CORTEX_A9
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#define PORT_ARCHITECTURE_ARM_CORTEXA9
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#define PORT_ARCHITECTURE_NAME "ARMv7"
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#define PORT_CORE_VARIANT_NAME "ARM Cortex-A9"
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#else
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#error "unknown or unsupported ARM core"
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#endif
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#define PORT_INFO "Pure THUMB mode"
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#endif /* !defined(_FROM_ASM_) */
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/*===========================================================================*/
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/* Module data structures and types. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/**
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* @brief Type of stack and memory alignment enforcement.
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* @note In this architecture the stack alignment is enforced to 64 bits.
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*/
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typedef uint64_t stkalign_t;
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/**
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* @brief Generic ARM register.
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*/
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typedef void *regarm_t;
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during an
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* interrupt handler.
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*/
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struct port_extctx {
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regarm_t spsr_irq;
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regarm_t lr_irq;
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t r12;
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regarm_t lr_usr;
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};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switch.
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*/
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struct port_intctx {
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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};
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/**
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* @brief Platform dependent part of the @p thread_t structure.
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* @details In this port the structure just holds a pointer to the
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* @p port_intctx structure representing the stack pointer
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* at context switch time.
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*/
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struct port_context {
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struct port_intctx *sp;
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};
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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/**
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* @brief Platform dependent part of the @p chThdCreateI() API.
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* @details This code usually setup the context switching frame represented
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* by an @p port_intctx structure.
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*/
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
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sizeof (struct port_intctx)); \
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(tp)->ctx.sp->r4 = (regarm_t)(pf); \
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(tp)->ctx.sp->r5 = (regarm_t)(arg); \
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(tp)->ctx.sp->lr = (regarm_t)(_port_thread_start); \
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}
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/**
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* @brief Computes the thread working area global size.
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* @note There is no need to perform alignments in this macro.
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*/
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#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
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sizeof(struct port_extctx) + \
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((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*
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* @param[in] s the name to be assigned to the stack array
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* @param[in] n the stack size to be assigned to the thread
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*/
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#define PORT_WORKING_AREA(s, n) \
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stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
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/**
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* @brief Priority level verification macro.
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* @todo Add the required parameters to armparams.h.
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*/
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#define PORT_IRQ_IS_VALID_PRIORITY(n) false
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/**
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* @brief IRQ prologue code.
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* @details This macro must be inserted at the start of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE()
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/**
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* @brief IRQ epilogue code.
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* @details This macro must be inserted at the end of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE() return chSchIsPreemptionRequired()
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/**
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* @brief IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#ifdef __cplusplus
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#define PORT_IRQ_HANDLER(id) extern "C" bool id(void)
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#else
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#define PORT_IRQ_HANDLER(id) bool id(void)
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#endif
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/**
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* @brief Fast IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_FAST_IRQ_HANDLER(id) \
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bool id(void)
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/**
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* @brief Performs a context switch between two threads.
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* @details This is the most critical code in any port, this function
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* is responsible for the context switch between 2 threads.
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* @note The implementation of this code affects <b>directly</b> the context
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* switch performance so optimize here as much as you can.
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* @note Implemented as inlined code for performance reasons.
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*
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* @param[in] ntp the thread to be switched in
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* @param[in] otp the thread to be switched out
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*/
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#if defined(THUMB)
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#if CH_DBG_ENABLE_STACK_CHECK == TRUE
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#define port_switch(ntp, otp) { \
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register struct port_intctx *r13 asm ("r13"); \
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if ((stkalign_t *)(r13 - 1) < otp->wabase) \
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chSysHalt("stack overflow"); \
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_port_switch_thumb(ntp, otp); \
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}
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#else
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#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp)
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#endif
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#else /* !defined(THUMB) */
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#if CH_DBG_ENABLE_STACK_CHECK == TRUE
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#define port_switch(ntp, otp) { \
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register struct port_intctx *r13 asm ("r13"); \
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if ((stkalign_t *)(r13 - 1) < otp->wabase) \
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chSysHalt("stack overflow"); \
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_port_switch_arm(ntp, otp); \
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}
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#else
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#define port_switch(ntp, otp) _port_switch_arm(ntp, otp)
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#endif
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#endif /* !defined(THUMB) */
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(THUMB_PRESENT)
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syssts_t _port_get_cpsr(void);
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#endif
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#if defined(THUMB)
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void _port_switch_thumb(thread_t *ntp, thread_t *otp);
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#else
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void _port_switch_arm(thread_t *ntp, thread_t *otp);
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#endif
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void _port_thread_start(void);
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#ifdef __cplusplus
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}
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#endif
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/*===========================================================================*/
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/* Module inline functions. */
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/*===========================================================================*/
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/**
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* @brief Port-related initialization code.
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*/
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static inline void port_init(void) {
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}
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/**
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* @brief Returns a word encoding the current interrupts status.
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*
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* @return The interrupts status.
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*/
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static inline syssts_t port_get_irq_status(void) {
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syssts_t sts;
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#if defined(THUMB)
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sts = _port_get_cpsr();
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#else
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__asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :);
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#endif
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/*lint -save -e530 [9.1] Asm instruction not seen by lint.*/
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return sts;
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/*lint -restore*/
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}
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/**
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* @brief Checks the interrupt status.
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*
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* @param[in] sts the interrupt status word
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*
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* @return The interrupt status.
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* @retval false the word specified a disabled interrupts status.
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* @retval true the word specified an enabled interrupts status.
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*/
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static inline bool port_irq_enabled(syssts_t sts) {
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return (sts & (syssts_t)0x40) == (syssts_t)0;
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}
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/**
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* @brief Determines the current execution context.
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*
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* @return The execution context.
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* @retval false not running in ISR mode.
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* @retval true running in ISR mode.
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*/
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static inline bool port_is_isr_context(void) {
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syssts_t sts;
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#if defined(THUMB)
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sts = _port_get_cpsr();
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#else
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__asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :);
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#endif
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/*lint -save -e530 [9.1] Asm instruction not seen by lint.*/
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return (sts & (syssts_t)0x1F) == (syssts_t)0x11;
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/*lint -restore*/
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}
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/**
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* @brief Kernel-lock action.
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* @details In this port it disables the FIQ and keep IRQ state.
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*/
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static inline void port_lock(void) {
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__asm volatile ("cpsid if" : : : "memory");
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}
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/**
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* @brief Kernel-unlock action.
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* @details In this port it enables the FIQ and IRQ sources.
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*/
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static inline void port_unlock(void) {
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__asm volatile ("cpsie if" : : : "memory");
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}
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/**
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* @brief Kernel-lock action from an interrupt handler.
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* @note Empty in this port.
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*/
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static inline void port_lock_from_isr(void) {
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}
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/**
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* @brief Kernel-unlock action from an interrupt handler.
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* @note Empty in this port.
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*/
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static inline void port_unlock_from_isr(void) {
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}
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/**
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* @brief Disables all the interrupt sources.
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* @details In this port it disables FIQ sources and keeps IRQ sources
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* disabled.
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*/
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static inline void port_disable(void) {
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__asm volatile ("msr CPSR_c, #0xDF" : : : "memory");
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}
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/**
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* @brief Disables the interrupt sources below kernel-level priority.
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* @note Interrupt sources above kernel level remains enabled.
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* @note In this port it disables the FIQ and IRQ sources.
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*/
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static inline void port_suspend(void) {
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__asm volatile ("msr CPSR_c, #0xDF" : : : "memory");
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}
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/**
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* @brief Enables all the interrupt sources.
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* @note In this port it enables the FIQ and IRQ sources.
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*/
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static inline void port_enable(void) {
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__asm volatile ("msr CPSR_c, #0x1F" : : : "memory");
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}
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/**
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* @brief Enters an architecture-dependent IRQ-waiting mode.
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* @details The function is meant to return when an interrupt becomes pending.
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* The simplest implementation is an empty function or macro but this
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* would not take advantage of architecture-specific power saving
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* modes.
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* @note Implemented as an inlined @p WFI instruction.
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*/
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static inline void port_wait_for_interrupt(void) {
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asm volatile ("wfi" : : : "memory");
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}
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/**
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* @brief Returns the current value of the realtime counter.
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*
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* @return The realtime counter value.
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*/
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static inline rtcnt_t port_rt_get_counter_value(void) {
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#if ((ARM_CORE == ARM_CORE_CORTEX_A5) || (ARM_CORE == ARM_CORE_CORTEX_A9) || defined(__DOXYGEN__))
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rtcnt_t cyc;
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__asm volatile("mrc p15, 0, %[p0], c9, c13, 0" : [p0] "=r" (cyc) :);
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return cyc;
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#else
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/*
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* TODO develop same function for ARM_CORE_CORTEX_A8
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*/
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return 0;
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#endif
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}
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#if CH_CFG_ST_TIMEDELTA > 0
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#if PORT_USE_ALT_TIMER == FALSE
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#include "chcore_timer.h"
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#else /* PORT_USE_ALT_TIMER */
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#include "chcore_timer_alt.h"
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#endif /* PORT_USE_ALT_TIMER */
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#endif /* CH_CFG_ST_TIMEDELTA > 0 */
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#endif /* !defined(_FROM_ASM_) */
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#endif /* CHCORE_H */
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/** @} */
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