164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.io/license.html
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*/
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/**
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* @file boards/addons/gdisp/board_HX8347D_stm32f4discovery.h
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* @brief GDISP Graphic Driver subsystem board SPI interface for the HX8347D display.
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*
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* @note This file contains a mix of hardware specific and operating system specific
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* code. You will need to change it for your CPU and/or operating system.
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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/* Pin assignments */
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#define SET_RST palSetPad(GPIOB, 8)
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#define CLR_RST palClearPad(GPIOB, 8)
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#define SET_DATA palSetPad(GPIOB, 9)
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#define CLR_DATA palClearPad(GPIOB, 9)
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#define SET_CS palSetPad(GPIOA, 4)
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#define CLR_CS palClearPad(GPIOA, 4)
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/* PWM configuration structure. We use timer 4 channel 2 (orange LED on board). */
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static const PWMConfig pwmcfg = {
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1000000, /* 1 MHz PWM clock frequency. */
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100, /* PWM period is 100 cycles. */
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0,
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{
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{PWM_OUTPUT_ACTIVE_HIGH, 0},
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{PWM_OUTPUT_ACTIVE_HIGH, 0},
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{PWM_OUTPUT_ACTIVE_HIGH, 0},
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{PWM_OUTPUT_ACTIVE_HIGH, 0}
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},
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0
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};
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/*
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* SPI1 configuration structure.
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* Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
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* The slave select line is the pin 4 on the port GPIOA.
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*/
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static const SPIConfig spi1cfg_8bit = {
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0,
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/* HW dependent part.*/
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GPIOA,
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4,
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0 //SPI_CR1_BR_0
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};
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/*
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* SPI1 configuration structure.
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* Speed 42MHz, CPHA=0, CPOL=0, 16bits frames, MSb transmitted first.
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* The slave select line is the pin 4 on the port GPIOA.
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*/
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static const SPIConfig spi1cfg_16bit = {
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0,
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/* HW dependent part.*/
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GPIOA,
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4,
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SPI_CR1_DFF //SPI_CR1_BR_0
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};
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static GFXINLINE void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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/* Display backlight control */
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/* TIM4 is an alternate function 2 (AF2) */
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pwmStart(&PWMD4, &pwmcfg);
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palSetPadMode(GPIOD, 13, PAL_MODE_ALTERNATE(2));
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pwmEnableChannel(&PWMD4, 1, 100);
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palSetPadMode(GPIOB, 8, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST); /* RST */
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palSetPadMode(GPIOB, 9, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST); /* RS */
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/*
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* Initializes the SPI driver 1. The SPI1 signals are routed as follow:
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* PB12 - NSS.
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* PB13 - SCK.
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* PB14 - MISO.
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* PB15 - MOSI.
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*/
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SET_CS; SET_DATA;
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spiStart(&SPID1, &spi1cfg_8bit);
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palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST); /* NSS. */
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palSetPadMode(GPIOA, 5, PAL_MODE_ALTERNATE(5)|PAL_STM32_OSPEED_HIGHEST); /* SCK. */
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palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(5)); /* MISO. */
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palSetPadMode(GPIOA, 7, PAL_MODE_ALTERNATE(5)|PAL_STM32_OSPEED_HIGHEST); /* MOSI. */
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break;
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}
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
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(void) g;
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if (state) {
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CLR_RST;
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} else {
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SET_RST;
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}
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}
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static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
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(void) g;
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pwmEnableChannel(&PWMD4, 1, percent);
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}
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static GFXINLINE void acquire_bus(GDisplay *g) {
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(void) g;
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spiAcquireBus(&SPID1);
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while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0)); // Safety
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CLR_CS;
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}
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static GFXINLINE void release_bus(GDisplay *g) {
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(void) g;
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SET_CS;
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spiReleaseBus(&SPID1);
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}
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static GFXINLINE void busmode16(GDisplay *g) {
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(void) g;
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spiStart(&SPID1, &spi1cfg_16bit);
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}
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static GFXINLINE void busmode8(GDisplay *g) {
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(void) g;
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spiStart(&SPID1, &spi1cfg_8bit);
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}
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static GFXINLINE void write_index(GDisplay *g, gU8 index) {
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(void) g;
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CLR_DATA;
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SPI1->DR = index;
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while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
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SET_DATA;
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}
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static GFXINLINE void write_data(GDisplay *g, gU8 data) {
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(void) g;
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SPI1->DR = data;
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while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
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}
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static GFXINLINE void write_ram16(GDisplay *g, gU16 data) {
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(void) g;
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SPI1->DR = data;
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while((SPI1->SR & SPI_SR_TXE) == 0);
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}
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#endif /* _GDISP_LLD_BOARD_H */
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