276 lines
11 KiB
C
276 lines
11 KiB
C
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/*
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ChibiOS - Copyright (C) 2014 Derek Mulcahy
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADCv1/hal_adc_lld.h
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* @brief KINETIS ADC subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef HAL_ADC_LLD_H_
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#define HAL_ADC_LLD_H_
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Minimum ADC clock frequency.
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*/
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#define KINETIS_ADCCLK_MIN 600000
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/**
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* @brief Maximum ADC clock frequency.
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*/
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#define KINETIS_ADCCLK_MAX 36000000
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#define ADCx_SC3_AVGS_AVERAGE_4_SAMPLES 0
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#define ADCx_SC3_AVGS_AVERAGE_8_SAMPLES 1
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#define ADCx_SC3_AVGS_AVERAGE_16_SAMPLES 2
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#define ADCx_SC3_AVGS_AVERAGE_32_SAMPLES 3
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#define ADCx_CFG1_ADIV_DIV_1 0
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#define ADCx_CFG1_ADIV_DIV_2 1
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#define ADCx_CFG1_ADIV_DIV_4 2
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#define ADCx_CFG1_ADIV_DIV_8 3
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#define ADCx_CFG1_ADIVCLK_BUS_CLOCK 0
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#define ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2 1
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#define ADCx_CFG1_ADIVCLK_BUS_ALTCLK 2
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#define ADCx_CFG1_ADIVCLK_BUS_ADACK 3
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#define ADCx_CFG1_MODE_8_OR_9_BITS 0
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#define ADCx_CFG1_MODE_12_OR_13_BITS 1
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#define ADCx_CFG1_MODE_10_OR_11_BITS 2
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#define ADCx_CFG1_MODE_16_BITS 3
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#define ADCx_SC1n_ADCH_DAD0 0
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#define ADCx_SC1n_ADCH_DAD1 1
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#define ADCx_SC1n_ADCH_DAD2 2
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#define ADCx_SC1n_ADCH_DAD3 3
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#define ADCx_SC1n_ADCH_DADP0 0
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#define ADCx_SC1n_ADCH_DADP1 1
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#define ADCx_SC1n_ADCH_DADP2 2
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#define ADCx_SC1n_ADCH_DADP3 3
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#define ADCx_SC1n_ADCH_AD4 4
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#define ADCx_SC1n_ADCH_AD5 5
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#define ADCx_SC1n_ADCH_AD6 6
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#define ADCx_SC1n_ADCH_AD7 7
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#define ADCx_SC1n_ADCH_AD8 8
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#define ADCx_SC1n_ADCH_AD9 9
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#define ADCx_SC1n_ADCH_AD10 10
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#define ADCx_SC1n_ADCH_AD11 11
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#define ADCx_SC1n_ADCH_AD12 12
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#define ADCx_SC1n_ADCH_AD13 13
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#define ADCx_SC1n_ADCH_AD14 14
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#define ADCx_SC1n_ADCH_AD15 15
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#define ADCx_SC1n_ADCH_AD16 16
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#define ADCx_SC1n_ADCH_AD17 17
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#define ADCx_SC1n_ADCH_AD18 18
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#define ADCx_SC1n_ADCH_AD19 19
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#define ADCx_SC1n_ADCH_AD20 20
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#define ADCx_SC1n_ADCH_AD21 21
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#define ADCx_SC1n_ADCH_AD22 22
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#define ADCx_SC1n_ADCH_AD23 23
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#define ADCx_SC1n_ADCH_TEMP_SENSOR 26
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#define ADCx_SC1n_ADCH_BANDGAP 27
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#define ADCx_SC1n_ADCH_VREFSH 29
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#define ADCx_SC1n_ADCH_VREFSL 30
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#define ADCx_SC1n_ADCH_DISABLED 31
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#define ADC_DAD0 (1 << ADCx_SC1n_ADCH_DAD0)
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#define ADC_DAD1 (1 << ADCx_SC1n_ADCH_DAD1)
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#define ADC_DAD2 (1 << ADCx_SC1n_ADCH_DAD2)
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#define ADC_DAD3 (1 << ADCx_SC1n_ADCH_DAD3)
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#define ADC_DADP0 (1 << ADCx_SC1n_ADCH_DADP0)
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#define ADC_DADP1 (1 << ADCx_SC1n_ADCH_DADP1)
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#define ADC_DADP2 (1 << ADCx_SC1n_ADCH_DADP2)
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#define ADC_DADP3 (1 << ADCx_SC1n_ADCH_DADP3)
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#define ADC_AD4 (1 << ADCx_SC1n_ADCH_AD4)
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#define ADC_AD5 (1 << ADCx_SC1n_ADCH_AD5)
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#define ADC_AD6 (1 << ADCx_SC1n_ADCH_AD6)
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#define ADC_AD7 (1 << ADCx_SC1n_ADCH_AD7)
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#define ADC_AD8 (1 << ADCx_SC1n_ADCH_AD8)
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#define ADC_AD9 (1 << ADCx_SC1n_ADCH_AD9)
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#define ADC_AD10 (1 << ADCx_SC1n_ADCH_AD10)
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#define ADC_AD11 (1 << ADCx_SC1n_ADCH_AD11)
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#define ADC_AD12 (1 << ADCx_SC1n_ADCH_AD12)
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#define ADC_AD13 (1 << ADCx_SC1n_ADCH_AD13)
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#define ADC_AD14 (1 << ADCx_SC1n_ADCH_AD14)
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#define ADC_AD15 (1 << ADCx_SC1n_ADCH_AD15)
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#define ADC_AD16 (1 << ADCx_SC1n_ADCH_AD16)
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#define ADC_AD17 (1 << ADCx_SC1n_ADCH_AD17)
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#define ADC_AD18 (1 << ADCx_SC1n_ADCH_AD18)
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#define ADC_AD19 (1 << ADCx_SC1n_ADCH_AD19)
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#define ADC_AD20 (1 << ADCx_SC1n_ADCH_AD20)
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#define ADC_AD21 (1 << ADCx_SC1n_ADCH_AD21)
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#define ADC_AD22 (1 << ADCx_SC1n_ADCH_AD22)
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#define ADC_AD23 (1 << ADCx_SC1n_ADCH_AD23)
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#define ADC_TEMP_SENSOR (1 << ADCx_SC1n_ADCH_TEMP_SENSOR)
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#define ADC_BANDGAP (1 << ADCx_SC1n_ADCH_BANDGAP)
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#define ADC_VREFSH (1 << ADCx_SC1n_ADCH_VREFSH)
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#define ADC_VREFSL (1 << ADCx_SC1n_ADCH_VREFSL)
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#define ADC_DISABLED (1 << ADCx_SC1n_ADCH_DISABLED)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief ADC1 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(KINETIS_ADC_USE_ADC0) || defined(__DOXYGEN__)
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#define KINETIS_ADC_USE_ADC0 FALSE
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#endif
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/**
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* @brief ADC interrupt priority level setting.
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*/
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#if !defined(KINETIS_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define KINETIS_ADC_IRQ_PRIORITY 5
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if KINETIS_ADC_USE_ADC0 && !KINETIS_HAS_ADC0
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#error "ADC1 not present in the selected device"
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#endif
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#if !KINETIS_ADC_USE_ADC0
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADC sample data type.
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*/
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typedef uint16_t adcsample_t;
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/**
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* @brief Channels number in a conversion group.
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*/
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typedef uint16_t adc_channels_num_t;
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/**
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* @brief Possible ADC failure causes.
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* @note Error codes are architecture dependent and should not relied
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* upon.
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*/
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typedef enum {
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ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
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ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
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} adcerror_t;
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/**
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* @brief Type of a structure representing an ADC driver.
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*/
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typedef struct hal_adc_driver ADCDriver;
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/**
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* @brief Low level fields of the ADC configuration structure.
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*/
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#define adc_lld_configuration_group_fields \
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/** \
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* @brief Bitmask of channels for ADC conversion. \
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*/ \
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uint32_t channel_mask; \
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/** \
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* @brief ADC CFG1 register initialization data. \
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* @note All the required bits must be defined into this field. \
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*/ \
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uint32_t cfg1; \
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/** \
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* @brief ADC SC3 register initialization data. \
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* @note All the required bits must be defined into this field. \
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*/ \
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uint32_t sc3;
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/**
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* @brief Low level fields of the ADC configuration structure.
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*/
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#define adc_lld_config_fields \
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/* Perform first time calibration */ \
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bool calibrate;
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/**
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* @brief Low level fields of the ADC driver structure.
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*/
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#define adc_lld_driver_fields \
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/* Pointer to the ADCx registers block.*/ \
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ADC_TypeDef *adc; \
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/* @brief Number of samples expected. */ \
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size_t number_of_samples; \
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/* @brief Current position in the buffer. */ \
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size_t current_index; \
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/* @brief Current channel index into group channel_mask. */ \
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size_t current_channel; \
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if KINETIS_ADC_USE_ADC0 && !defined(__DOXYGEN__)
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extern ADCDriver ADCD1;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void adc_lld_init(void);
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void adc_lld_start(ADCDriver *adcp);
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void adc_lld_stop(ADCDriver *adcp);
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void adc_lld_start_conversion(ADCDriver *adcp);
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void adc_lld_stop_conversion(ADCDriver *adcp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_ADC */
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#endif /* HAL_ADC_LLD_H_ */
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/** @} */
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