71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
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/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.io/license.html
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*/
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#ifndef _STMPE610_H
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#define _STMPE610_H
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// Identification registers
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#define STMPE610_REG_CHP_ID 0x00 // 16-bit
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#define STMPE610_REG_ID_VER 0x02
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// System registers
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#define STMPE610_REG_SYS_CTRL1 0x03
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#define STMPE610_REG_SYS_CTRL2 0x04
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#define STMPE610_REG_SPI_CFG 0x08
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// Interrupt control registers
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#define STMPE610_REG_INT_CTRL 0x09
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#define STMPE610_REG_INT_EN 0x0A
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#define STMPE610_REG_INT_STA 0x0B
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#define STMPE610_REG_GPIO_INT_EN 0x0C
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#define STMPE610_REG_GPIO_INT_STA 0x0D
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#define STMPE610_REG_ADC_INT_EN 0x0E
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#define STMPE610_REG_ADC_INT_STA 0x0F
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// GPIO registers
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#define STMPE610_REG_GPIO_SET_PIN 0x10
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#define STMPE610_REG_GPIO_CLR_PIN 0x11
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#define STMPE610_REG_GPIO_MP_STA 0x12
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#define STMPE610_REG_GPIO_DIR 0x13
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#define STMPE610_REG_GPIO_ED 0x14
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#define STMPE610_REG_GPIO_RE 0x15
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#define STMPE610_REG_GPIO_FE 0x16
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#define STMPE610_REG_GPIO_AF 0x17
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// ADC registers
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#define STMPE610_REG_ADC_CTRL1 0x20
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#define STMPE610_REG_ADC_CTRL2 0x21
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#define STMPE610_REG_ADC_CAPT 0x22
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#define STMPE610_REG_ADC_DATA_CH0 0x30 // 16-bit
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#define STMPE610_REG_ADC_DATA_CH1 0x32 // 16-bit
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#define STMPE610_REG_ADC_DATA_CH4 0x38 // 16-bit
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#define STMPE610_REG_ADC_DATA_CH5 0x3A // 16-bit
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#define STMPE610_REG_ADC_DATA_CH6 0x3C // 16-bit
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#define STMPE610_REG_ADC_DATA_CH7 0x3E // 16-bit
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// Touchscreen registers
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#define STMPE610_REG_TSC_CTRL 0x40
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#define STMPE610_REG_TSC_CFG 0x41
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#define STMPE610_REG_WDW_TR_X 0x42 // 16-bit
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#define STMPE610_REG_WDW_TR_Y 0x44 // 16-bit
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#define STMPE610_REG_WDW_BL_X 0x46 // 16-bit
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#define STMPE610_REG_WDW_BL_Y 0x48 // 16-bit
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#define STMPE610_REG_FIFO_TH 0x4A
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#define STMPE610_REG_FIFO_STA 0x4B
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#define STMPE610_REG_FIFO_SIZE 0x4C
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#define STMPE610_REG_TSC_DATA_X 0x4D // 16-bit
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#define STMPE610_REG_TSC_DATA_Y 0x4F // 16-bit
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#define STMPE610_REG_TSC_DATA_Z 0x51
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#define STMPE610_REG_TSC_DATA_XYZ 0x52 // 32-bit
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#define STMPE610_REG_TSC_FRACT_XYZ 0x56
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#define STMPE610_REG_TSC_DATA 0x57
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#define STMPE610_REG_TSC_I_DRIVE 0x58
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#define STMPE610_REG_TSC_SHIELD 0x59
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#endif /* _STMPE610_H */
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