464 lines
19 KiB
C
464 lines
19 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32H7xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32H7xx_MCUCONF
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#define STM32H743_MCUCONF
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#define STM32H753_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSICLK
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/*
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* Memory attributes settings.
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*/
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#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
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#define STM32_NOCACHE_SRAM3 TRUE
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/*
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* PWR system settings.
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* Reading STM32 Reference Manual is required.
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* Register constants are taken from the ST header.
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*/
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
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#define STM32_PWR_CR2 (PWR_CR2_BREN)
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#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
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#define STM32_PWR_CPUCR 0
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/*
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* Clock tree static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_CSI_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_HSIDIV STM32_HSIDIV_DIV1
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/*
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* PLLs static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
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#define STM32_PLLCFGR_MASK ~0
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#define STM32_PLL1_ENABLED TRUE
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#define STM32_PLL1_P_ENABLED TRUE
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#define STM32_PLL1_Q_ENABLED TRUE
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#define STM32_PLL1_R_ENABLED TRUE
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#define STM32_PLL1_DIVM_VALUE 4
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#define STM32_PLL1_DIVN_VALUE 400
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#define STM32_PLL1_FRACN_VALUE 0
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 8
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#define STM32_PLL2_ENABLED TRUE
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#define STM32_PLL2_P_ENABLED TRUE
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#define STM32_PLL2_Q_ENABLED TRUE
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#define STM32_PLL2_R_ENABLED TRUE
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#define STM32_PLL2_DIVM_VALUE 4
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#define STM32_PLL2_DIVN_VALUE 400
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#define STM32_PLL2_FRACN_VALUE 0
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#define STM32_PLL2_DIVP_VALUE 40
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#define STM32_PLL2_DIVQ_VALUE 8
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#define STM32_PLL2_DIVR_VALUE 8
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#define STM32_PLL3_ENABLED TRUE
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#define STM32_PLL3_P_ENABLED TRUE
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#define STM32_PLL3_Q_ENABLED TRUE
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#define STM32_PLL3_R_ENABLED TRUE
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#define STM32_PLL3_DIVM_VALUE 4
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#define STM32_PLL3_DIVN_VALUE 400
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#define STM32_PLL3_FRACN_VALUE 0
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#define STM32_PLL3_DIVP_VALUE 8
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#define STM32_PLL3_DIVQ_VALUE 8
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#define STM32_PLL3_DIVR_VALUE 8
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/*
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* Core clocks dynamic settings (can be changed at runtime).
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_SW STM32_SW_PLL1_P_CK
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#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
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#define STM32_D1CPRE STM32_D1CPRE_DIV1
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#define STM32_D1HPRE STM32_D1HPRE_DIV4
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#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
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#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
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#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
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#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
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/*
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* Peripherals clocks static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
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#define STM32_MCO1PRE_VALUE 4
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#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
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#define STM32_MCO2PRE_VALUE 4
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#define STM32_TIMPRE_ENABLE TRUE
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#define STM32_HRTIMSEL 0
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#define STM32_STOPKERWUCK 0
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#define STM32_STOPWUCK 0
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#define STM32_RTCPRE_VALUE 8
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#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
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#define STM32_QSPISEL STM32_QSPISEL_HCLK
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#define STM32_FMCSEL STM32_QSPISEL_HCLK
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#define STM32_SWPSEL STM32_SWPSEL_PCLK1
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#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
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#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
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#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
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#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
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#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
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#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
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#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_CECSEL STM32_CECSEL_LSE_CK
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#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK
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#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
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#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
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#define STM32_USART16SEL STM32_USART16SEL_PCLK2
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#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
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#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
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#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
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#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
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#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
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#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_PRIORITY 15
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#define STM32_IRQ_EXTI22_PRIORITY 15
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_DUAL_MODE FALSE
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC12 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
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#define STM32_ADC_ADC12_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC3_IRQ_PRIORITY 5
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_USE_CAN2 FALSE
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#define STM32_CAN_USE_CAN3 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11
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#define STM32_CAN_CAN2_IRQ_PRIORITY 11
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#define STM32_CAN_CAN3_IRQ_PRIORITY 11
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY 7
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#define STM32_GPT_TIM2_IRQ_PRIORITY 7
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#define STM32_GPT_TIM3_IRQ_PRIORITY 7
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#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#define STM32_GPT_TIM5_IRQ_PRIORITY 7
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#define STM32_GPT_TIM6_IRQ_PRIORITY 7
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#define STM32_GPT_TIM7_IRQ_PRIORITY 7
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#define STM32_GPT_TIM8_IRQ_PRIORITY 7
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#define STM32_GPT_TIM9_IRQ_PRIORITY 7
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#define STM32_GPT_TIM11_IRQ_PRIORITY 7
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#define STM32_GPT_TIM12_IRQ_PRIORITY 7
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#define STM32_GPT_TIM14_IRQ_PRIORITY 7
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_USE_I2C4 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
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#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 7
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#define STM32_ICU_TIM5_IRQ_PRIORITY 7
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#define STM32_ICU_TIM8_IRQ_PRIORITY 7
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#define STM32_ICU_TIM9_IRQ_PRIORITY 7
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/*
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* MAC driver system settings.
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*/
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#define STM32_MAC_TRANSMIT_BUFFERS 2
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#define STM32_MAC_RECEIVE_BUFFERS 4
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#define STM32_MAC_BUFFERS_SIZE 1522
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#define STM32_MAC_PHY_TIMEOUT 100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY 13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM4 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM5 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM8 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM9 FALSE
|
||
|
|
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* RTC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_RTC_PRESA_VALUE 32
|
||
|
|
#define STM32_RTC_PRESS_VALUE 1024
|
||
|
|
#define STM32_RTC_CR_INIT 0
|
||
|
|
#define STM32_RTC_TAMPCR_INIT 0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SDC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SDC_USE_SDMMC1 FALSE
|
||
|
|
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
|
||
|
|
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
|
||
|
|
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
|
||
|
|
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
|
||
|
|
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
|
||
|
|
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SERIAL driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SERIAL_USE_USART1 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART2 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART3 TRUE
|
||
|
|
#define STM32_SERIAL_USE_UART4 FALSE
|
||
|
|
#define STM32_SERIAL_USE_UART5 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART6 FALSE
|
||
|
|
#define STM32_SERIAL_USE_UART7 FALSE
|
||
|
|
#define STM32_SERIAL_USE_UART8 FALSE
|
||
|
|
#define STM32_SERIAL_USART1_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART2_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART3_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART4_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART5_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART6_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART7_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART8_PRIORITY 12
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SPI driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SPI_USE_SPI1 TRUE
|
||
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI3 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI4 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI5 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI6 FALSE
|
||
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
|
||
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ST driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ST_IRQ_PRIORITY 8
|
||
|
|
#define STM32_ST_USE_TIMER 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* UART driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_UART_USE_USART1 FALSE
|
||
|
|
#define STM32_UART_USE_USART2 FALSE
|
||
|
|
#define STM32_UART_USE_USART3 FALSE
|
||
|
|
#define STM32_UART_USE_UART4 FALSE
|
||
|
|
#define STM32_UART_USE_UART5 FALSE
|
||
|
|
#define STM32_UART_USE_USART6 FALSE
|
||
|
|
#define STM32_UART_USE_UART7 FALSE
|
||
|
|
#define STM32_UART_USE_UART8 FALSE
|
||
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||
|
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART7_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART8_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* USB driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_USB_USE_OTG1 FALSE
|
||
|
|
#define STM32_USB_USE_OTG2 FALSE
|
||
|
|
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||
|
|
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||
|
|
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* WDG driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_WDG_USE_IWDG FALSE
|
||
|
|
|
||
|
|
#endif /* MCUCONF_H */
|