245 lines
7.8 KiB
C
245 lines
7.8 KiB
C
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/*
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ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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SDRAM routines added by Nick Klimov aka progfin.
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*/
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/**
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* @file hal_sdram.h
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* @brief SDRAM Driver subsystem low level driver header.
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*
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* @addtogroup SDRAM
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* @{
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*/
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#ifndef HAL_SDRAM_H_
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#define HAL_SDRAM_H_
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#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*
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* FMC SDRAM Mode definition register defines
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*/
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#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/*
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* FMC_ReadPipe_Delay
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*/
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#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
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#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
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#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
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#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
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/*
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* FMC_Read_Burst
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*/
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#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
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#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
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#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
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/*
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* FMC_SDClock_Period
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*/
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#define FMC_SDClock_Disable ((uint32_t)0x00000000)
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#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
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#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
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#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
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/*
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* FMC_ColumnBits_Number
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*/
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#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
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#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
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#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
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#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
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/*
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* FMC_RowBits_Number
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*/
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#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
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#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
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#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
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/*
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* FMC_SDMemory_Data_Width
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*/
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#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
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#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
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#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
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/*
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* FMC_InternalBank_Number
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*/
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#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
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#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
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/*
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* FMC_CAS_Latency
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*/
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#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
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#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
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#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
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/*
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* FMC_Write_Protection
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*/
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#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
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#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SDRAM driver enable switch.
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* @details If set to @p TRUE the support for SDRAM1 is included.
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*/
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#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__)
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#define STM32_SDRAM_USE_SDRAM1 FALSE
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#else
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#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
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#endif
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/**
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* @brief SDRAM driver enable switch.
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* @details If set to @p TRUE the support for SDRAM2 is included.
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*/
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#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__)
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#define STM32_SDRAM_USE_SDRAM2 FALSE
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#else
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#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2
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#error "SDRAM driver activated but no SDRAM peripheral assigned"
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#endif
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#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC
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#error "FMC not present in the selected device"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Driver state machine possible states.
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*/
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typedef enum {
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SDRAM_UNINIT = 0, /**< Not initialized. */
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SDRAM_STOP = 1, /**< Stopped. */
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SDRAM_READY = 2, /**< Ready. */
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} sdramstate_t;
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/**
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* @brief Type of a structure representing an SDRAM driver.
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*/
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typedef struct SDRAMDriver SDRAMDriver;
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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/**
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* @brief SDRAM control register.
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* @note Its value will be used for both banks.
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*/
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uint32_t sdcr;
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/**
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* @brief SDRAM timing register.
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* @note Its value will be used for both banks.
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*/
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uint32_t sdtr;
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/**
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* @brief SDRAM command mode register.
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* @note Only its MRD and NRFS bits will be used.
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*/
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uint32_t sdcmr;
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/**
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* @brief SDRAM refresh timer register.
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* @note Only its COUNT bits will be used.
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*/
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uint32_t sdrtr;
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} SDRAMConfig;
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/**
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* @brief Structure representing an SDRAM driver.
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*/
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struct SDRAMDriver {
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/**
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* @brief Driver state.
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*/
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sdramstate_t state;
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/**
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* @brief Pointer to the FMC SDRAM registers block.
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*/
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FSMC_SDRAM_TypeDef *sdram;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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extern SDRAMDriver SDRAMD1;
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#ifdef __cplusplus
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extern "C" {
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#endif
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void sdramInit(void);
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void sdramObjectInit(SDRAMDriver *sdramp);
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void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
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void sdramStop(SDRAMDriver *sdramp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_SDRAM */
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#endif /* HAL_SDRAM_H_ */
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/** @} */
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