274 lines
12 KiB
C
274 lines
12 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* SPC560Bxx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 1...15 Lowest...Highest.
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* DMA priorities:
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* 0...15 Highest...Lowest.
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*/
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#define SPC560Bxx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define SPC5_NO_INIT FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_DISABLE_WATCHDOG TRUE
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#define SPC5_FMPLL0_IDF_VALUE 1
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#define SPC5_FMPLL0_NDIV_VALUE 32
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_XOSCDIV_VALUE 1
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#define SPC5_IRCDIV_VALUE 1
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#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
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#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
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#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
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#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
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#define SPC5_EMIOS0_GPRE_VALUE 20
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#define SPC5_EMIOS1_GPRE_VALUE 20
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/*
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* EDMA driver settings.
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*/
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#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
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EDMA_CR_GRP0PRI(0) | \
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EDMA_CR_EMLM | \
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EDMA_CR_ERGA)
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#define SPC5_EDMA_GROUP0_PRIORITIES 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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#define SPC5_EDMA_ERROR_IRQ_PRIO 12
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#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
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/*
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* SERIAL driver system settings.
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*/
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#define SPC5_SERIAL_USE_LINFLEX0 TRUE
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#define SPC5_SERIAL_USE_LINFLEX1 FALSE
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#define SPC5_SERIAL_USE_LINFLEX2 FALSE
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#define SPC5_SERIAL_USE_LINFLEX3 FALSE
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#define SPC5_SERIAL_USE_LINFLEX4 FALSE
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#define SPC5_SERIAL_USE_LINFLEX5 FALSE
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#define SPC5_SERIAL_USE_LINFLEX6 FALSE
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#define SPC5_SERIAL_USE_LINFLEX7 FALSE
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#define SPC5_SERIAL_USE_LINFLEX8 FALSE
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#define SPC5_SERIAL_USE_LINFLEX9 FALSE
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#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX2_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX3_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX4_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX5_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX6_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX7_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX8_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX9_PRIORITY 8
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/*
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* SPI driver system settings.
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*/
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#define SPC5_SPI_USE_DSPI0 FALSE
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#define SPC5_SPI_USE_DSPI1 FALSE
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#define SPC5_SPI_USE_DSPI2 FALSE
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#define SPC5_SPI_USE_DSPI3 FALSE
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#define SPC5_SPI_USE_DSPI4 FALSE
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#define SPC5_SPI_USE_DSPI5 FALSE
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#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_RX_ONLY
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#define SPC5_SPI_DSPI0_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3 | SPC5_MCR_PCSIS4 | SPC5_MCR_PCSIS5)
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#define SPC5_SPI_DSPI1_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3 | SPC5_MCR_PCSIS4)
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#define SPC5_SPI_DSPI2_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3)
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#define SPC5_SPI_DSPI3_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1)
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#define SPC5_SPI_DSPI4_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1)
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#define SPC5_SPI_DSPI5_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1)
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#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
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#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
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#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
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#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
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#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
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#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
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#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
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#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
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#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
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#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
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#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
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#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
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#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
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#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
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#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
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#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID 4
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#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID 5
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#define SPC5_SPI_DSPI5_RX_DMA_CH_ID 6
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#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI0_IRQ_PRIO 10
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#define SPC5_SPI_DSPI1_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_IRQ_PRIO 10
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#define SPC5_SPI_DSPI3_IRQ_PRIO 10
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#define SPC5_SPI_DSPI4_IRQ_PRIO 10
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#define SPC5_SPI_DSPI5_IRQ_PRIO 10
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#define SPC5_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DSPI DMA failure")
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/*
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* ICU-PWM driver system settings.
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*/
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#define SPC5_ICU_USE_EMIOS0_CH0 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH1 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH2 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH3 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH4 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH5 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH6 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH7 FALSE
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#define SPC5_ICU_USE_EMIOS0_CH24 FALSE
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#define SPC5_PWM_USE_EMIOS0_GROUP0 FALSE
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#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE
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#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 8
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#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 8
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#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_ICU_USE_EMIOS1_CH24 FALSE
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#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE
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#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE
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#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE
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#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 8
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#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 8
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#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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/*
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* CAN driver system settings.
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*/
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#define SPC5_CAN_USE_FILTERS FALSE
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#define SPC5_CAN_USE_FLEXCAN0 FALSE
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#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK FALSE
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#define SPC5_CAN_FLEXCAN0_PRIORITY 11
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#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_CAN_USE_FLEXCAN1 FALSE
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#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK FALSE
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#define SPC5_CAN_FLEXCAN1_PRIORITY 11
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#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_CAN_USE_FLEXCAN2 FALSE
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#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK FALSE
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#define SPC5_CAN_FLEXCAN2_PRIORITY 11
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#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_CAN_USE_FLEXCAN3 FALSE
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#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK FALSE
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#define SPC5_CAN_FLEXCAN3_PRIORITY 11
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#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_CAN_USE_FLEXCAN4 FALSE
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#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK FALSE
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#define SPC5_CAN_FLEXCAN4_PRIORITY 11
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#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_CAN_USE_FLEXCAN5 FALSE
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#define SPC5_CAN_FLEXCAN5_PRIORITY 11
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#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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/*
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* ADC driver system settings.
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*/
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#define SPC5_ADC_USE_ADC0 FALSE
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#define SPC5_ADC_ADC0_CLK_FREQUENCY HALF_PERIPHERAL_SET_CLOCK_FREQUENCY
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#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF FALSE
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#define SPC5_ADC_ADC0_WD_PRIORITY 12
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#define SPC5_ADC_ADC0_DMA_CH_ID 1
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#define SPC5_ADC_ADC0_DMA_IRQ_PRIO 12
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#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_ADC_USE_ADC1 FALSE
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#define SPC5_ADC_ADC1_CLK_FREQUENCY HALF_PERIPHERAL_SET_CLOCK_FREQUENCY
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#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF FALSE
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#define SPC5_ADC_ADC1_WD_PRIORITY 12
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#define SPC5_ADC_ADC1_DMA_CH_ID 2
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#define SPC5_ADC_ADC1_DMA_IRQ_PRIO 12
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#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#endif /* MCUCONF_H */
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