365 lines
13 KiB
C
365 lines
13 KiB
C
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/*
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ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file hal_fsmc.h
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* @brief FSMC Driver subsystem low level driver header.
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*
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* @addtogroup FSMC
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* @{
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*/
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#ifndef HAL_FSMC_H_
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#define HAL_FSMC_H_
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#include "hal.h"
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#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*
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* (Re)define if needed base address constants supplied in ST's CMSIS
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*/
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F745xx) || defined(STM32F746xx) || \
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defined(STM32F756xx) || defined(STM32F767xx) || \
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defined(STM32F769xx) || defined(STM32F777xx) || \
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defined(STM32F779xx))
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#if !defined(FSMC_Bank1_R_BASE)
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#define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
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#endif
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#if !defined(FSMC_Bank1E_R_BASE)
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#define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
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#endif
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#if !defined(FSMC_Bank2_R_BASE)
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#define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
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#endif
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#if !defined(FSMC_Bank3_R_BASE)
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#define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
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#endif
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#if !defined(FSMC_Bank4_R_BASE)
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#define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
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#endif
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#if !defined(FSMC_Bank5_R_BASE)
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#define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
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#endif
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#else
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#if !defined(FSMC_Bank1_R_BASE)
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#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
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#endif
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#if !defined(FSMC_Bank1E_R_BASE)
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#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
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#endif
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#if !defined(FSMC_Bank2_R_BASE)
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#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
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#endif
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#if !defined(FSMC_Bank3_R_BASE)
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#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
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#endif
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#if !defined(FSMC_Bank4_R_BASE)
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#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
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#endif
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#endif
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/*
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* Base bank mappings
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*/
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#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000)
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#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000)
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#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
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#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F7))
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#define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000)
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#define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000)
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#endif
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/*
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* Subbunks of bank1
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*/
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#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
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#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
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#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
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#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
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#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
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/*
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* Bank 2 (NAND)
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*/
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#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0)
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#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000)
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#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0)
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#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000)
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#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000)
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#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0)
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#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000)
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#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000)
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/*
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* Bank 3 (NAND)
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*/
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#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0)
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#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000)
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#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0)
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#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000)
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#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000)
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#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0)
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#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000)
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#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000)
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/*
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* Bank 4 (PC card)
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*/
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#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0)
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#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000)
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#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000)
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/*
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* More convenient typedefs than CMSIS has
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*/
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typedef struct {
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__IO uint32_t PCR; /**< NAND Flash control */
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__IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */
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__IO uint32_t PMEM; /**< NAND Flash Common memory space timing */
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__IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */
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uint32_t RESERVED0; /**< Reserved, 0x70 */
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__IO uint32_t ECCR; /**< NAND Flash ECC result registers */
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} FSMC_NAND_TypeDef;
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typedef struct {
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__IO uint32_t PCR; /**< PC Card control */
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__IO uint32_t SR; /**< PC Card FIFO status and interrupt */
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__IO uint32_t PMEM; /**< PC Card Common memory space timing */
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__IO uint32_t PATT; /**< PC Card Attribute memory space timing */
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__IO uint32_t PIO; /**< PC Card I/O space timing */
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} FSMC_PCCard_TypeDef;
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typedef struct {
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__IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
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__IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
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uint32_t RESERVED[63]; /**< Reserved */
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__IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
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} FSMC_SRAM_TypeDef;
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F7))
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typedef struct {
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__IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */
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__IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */
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__IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */
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__IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */
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__IO uint32_t SDCMR; /**< SDRAM comand mode register */
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__IO uint32_t SDRTR; /**< SDRAM refresh timer register */
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__IO uint32_t SDSR; /**< SDRAM status register */
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} FSMC_SDRAM_TypeDef;
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#endif
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/**
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* @brief PCR register
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*/
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#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1)
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#define FSMC_PCR_PBKEN ((uint32_t)1 << 2)
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#define FSMC_PCR_PTYP ((uint32_t)1 << 3)
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#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4)
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#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4)
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#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4)
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#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4)
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#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4)
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#define FSMC_PCR_ECCEN ((uint32_t)1 << 6)
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#define FSMC_PCR_PTYP_PCCARD 0
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#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP
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/**
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* @brief SR register
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*/
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#define FSMC_SR_IRS ((uint8_t)0x01)
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#define FSMC_SR_ILS ((uint8_t)0x02)
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#define FSMC_SR_IFS ((uint8_t)0x04)
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#define FSMC_SR_IREN ((uint8_t)0x08)
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#define FSMC_SR_ILEN ((uint8_t)0x10)
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#define FSMC_SR_IFEN ((uint8_t)0x20)
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#define FSMC_SR_FEMPT ((uint8_t)0x40)
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#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
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/**
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* @brief BCR register
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*/
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#define FSMC_BCR_MBKEN ((uint32_t)1 << 0)
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#define FSMC_BCR_MUXEN ((uint32_t)1 << 1)
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#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2)
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#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2)
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#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2)
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#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2)
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#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4)
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#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F7))
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#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
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#else
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#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
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#endif
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#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4)
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#define FSMC_BCR_FACCEN ((uint32_t)1 << 6)
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#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8)
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#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9)
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#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10)
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#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11)
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#define FSMC_BCR_WREN ((uint32_t)1 << 12)
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#define FSMC_BCR_WAITEN ((uint32_t)1 << 13)
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#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14)
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#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15)
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#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
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#if (defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F7))
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#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
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#endif
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#if (defined(STM32F7))
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#define FSMC_BCR_WFDIS ((uint32_t)1 << 21)
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#endif
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief FSMC driver enable switch.
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* @details If set to @p TRUE the support for FSMC is included.
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*/
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#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__)
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#define STM32_FSMC_USE_FSMC1 FALSE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !STM32_FSMC_USE_FSMC1
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#error "FSMC driver activated but no FSMC peripheral assigned"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a structure representing an FSMC driver.
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*/
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typedef struct FSMCDriver FSMCDriver;
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/**
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* @brief Driver state machine possible states.
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*/
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typedef enum {
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FSMC_UNINIT = 0, /**< Not initialized. */
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FSMC_STOP = 1, /**< Stopped. */
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FSMC_READY = 2, /**< Ready. */
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} fsmcstate_t;
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/**
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* @brief Structure representing an FSMC driver.
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*/
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struct FSMCDriver {
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/**
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* @brief Driver state.
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*/
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fsmcstate_t state;
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/* End of the mandatory fields.*/
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#if HAL_USE_SRAM
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#if STM32_SRAM_USE_SRAM1
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FSMC_SRAM_TypeDef *sram1;
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#endif
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#if STM32_SRAM_USE_SRAM2
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FSMC_SRAM_TypeDef *sram2;
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#endif
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#if STM32_SRAM_USE_SRAM3
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FSMC_SRAM_TypeDef *sram3;
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#endif
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#if STM32_SRAM_USE_SRAM4
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FSMC_SRAM_TypeDef *sram4;
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#endif
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||
|
|
#endif
|
||
|
|
|
||
|
|
#if HAL_USE_NAND
|
||
|
|
#if STM32_NAND_USE_NAND1
|
||
|
|
FSMC_NAND_TypeDef *nand1;
|
||
|
|
#endif
|
||
|
|
#if STM32_NAND_USE_NAND1
|
||
|
|
FSMC_NAND_TypeDef *nand2;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
|
||
|
|
defined(STM32F429xx) || defined(STM32F439xx) || \
|
||
|
|
defined(STM32F7))
|
||
|
|
#if HAL_USE_SDRAM
|
||
|
|
FSMC_SDRAM_TypeDef *sdram;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* Driver macros. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* External declarations. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__)
|
||
|
|
extern FSMCDriver FSMCD1;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
void fsmcInit(void);
|
||
|
|
void fsmcStart(FSMCDriver *fsmcp);
|
||
|
|
void fsmcStop(FSMCDriver *fsmcp);
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* HAL_USE_FSMC */
|
||
|
|
|
||
|
|
#endif /* HAL_FSMC_H_ */
|
||
|
|
|
||
|
|
/** @} */
|